Stacked Microelectronic Package with Conductive Vias
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Solution Overview
Problem
Existing microelectronic package stacking technologies face challenges in reducing parasitic effects due to long conductive structures between stacked chips, which hinder efficient area utilization and increase the overall height of the package.
Innovation Solution
The solution involves fabricating microelectronic packages with vertically stacked microelectronic units, where each unit includes semiconductor chips attached with adhesive layers and encapsulated with dielectric material, featuring conductive vias and terminals that allow for efficient electrical connection without the need for a package substrate, enabling reduced height and parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If microelectronic packages are stacked to save space, then area utilization is improved, but parasitic effects increase due to long conductive structures
Solution Approach 1:
The patent transitions from planar conductive connections to three-dimensional vertical connections through conductive vias that pass through the substrate thickness. This dimensional change allows chips to be stacked vertically with direct through-substrate connections, reducing the horizontal conductive path length and associated parasitic effects while maintaining compact area utilization.
Solution Approach 2:
The patent extracts and eliminates the package substrate from the traditional packaging structure. By removing the substrate that typically requires long conductive traces, the invention directly connects stacked chips through short conductive vias, thereby eliminating the source of parasitic inductance and resistance associated with long conductive paths.
2Reliability
If package substrate is used for connecting stacked chips, then electrical connection is achieved, but overall package height increases
Solution Approach 1:
The patent removes the package substrate entirely from the stacked chip structure. Instead of using a substrate-based connection approach that increases height, the invention implements direct chip-to-chip connections through conductive vias that pass through the chips themselves, eliminating the additional height contribution from a separate substrate layer.
Solution Approach 2:
The patent merges the connection function directly into the chip structure by integrating conductive vias within the chip layers themselves. This consolidation eliminates the need for a separate package substrate, reducing the overall package height while maintaining reliable electrical connections between stacked chips.
3Area of stationary object
If chips are stacked before testing, then area utilization is maximized, but testing capability is lost
Solution Approach 1:
The patent performs chip testing at the individual chip level before the stacking process. By conducting tests on bare chips prior to assembly, the invention ensures quality control is maintained while still achieving the area savings of stacked packaging. This preliminary testing approach allows defective chips to be identified and removed before they are integrated into the final stacked package.
Data Source
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AI summary
A microelectronic package (10) may include a first microelectronic unit (12) including a semiconductor chip (16A) having first chip contacts (28), an encapsulant (30) contacting an edge of the semiconductor chip, and first unit contacts (42) exposed at a surface of the encapsulant (30) and electrically connected with the first chip contacts (28). The package (10) may include a second microelectronic unit (14) including a semiconductor chip (16C) having second chip contacts (28C) at a surface thereof, and an encapsulant (54) contacting an edge of the chip of the second unit (14) and having a surface extending away from the edge. The surfaces of the chip (16C) and the encapsulant (54) of the second unit (14) define a face of the second unit. Package terminals (76) at the face may be electrically connected with the first unit contacts (42) through bond wires (100) electrically connected with the first unit contacts (42), and the second chip contacts (28C) through metallized vias (72) and traces (74) formed in contact with the second chip contacts (28C).