Stacked Microelectronic Packages with Interconnect Buffer Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current Fan-Out Wafer Level Packaging (FO-WLP) methods face challenges in efficiently integrating stacked microelectronic devices with high interconnectivity and compact packaging, limiting the density and complexity of microelectronic packages.
Innovation Solution
The method involves embedding stacked semiconductor die in a molded body with an intervening die attach material, forming interconnect buffer layers, and building redistribution layers (RDL) to create a highly interconnected package structure, allowing for additional microelectronic devices to be integrated and interconnected within a compact, molded body.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional FO-WLP methods are used to package microelectronic devices, then the packaging process is simple and well-established, but the device density and interconnectivity are limited
Solution Approach 1:
The patent transitions from traditional planar packaging to three-dimensional stacked packaging, where multiple semiconductor die are vertically stacked and interconnected through through-silicon vias (TSVs). This dimensional change enables significantly higher device density within the same footprint area while maintaining manufacturability through established semiconductor fabrication processes.
Solution Approach 2:
The patent implements nested packaging structures where smaller semiconductor die are embedded within a larger package substrate, and multiple layers are nested vertically. The package includes a substrate with first die, second die stacked thereon, and additional components nested within the same package body, creating a compact hierarchical structure that increases density without proportionally increasing complexity.
2Productivity
If stacked microelectronic devices are integrated to increase density, then the interconnectivity and device complexity increase, but the manufacturing process becomes more difficult
Solution Approach 1:
The patent performs preliminary actions by pre-forming through-silicon vias (TSVs) and interconnect structures on the semiconductor die before stacking. The package substrate is also pre-prepared with embedded conductors and insulation layers. These preliminary preparations enable subsequent stacking and bonding operations to proceed efficiently without requiring complex post-assembly interconnection processes.
Solution Approach 2:
The patent divides the package into separable modules: individual semiconductor die with integrated TSVs, a package substrate with pre-formed conductors, and optional additional components. Each module can be fabricated and tested independently using standard semiconductor processes, then assembled through bonding. This segmentation reduces manufacturing complexity compared to attempting to create all interconnections in a single monolithic structure.
3Reliability
If multiple RDL layers and TSVs are formed to achieve high interconnectivity, then electrical connectivity improves, but the manufacturing precision requirements increase
Solution Approach 1:
The patent introduces an intermediary package substrate that provides a stable platform with pre-formed conductors and insulation layers. This substrate acts as a mediator between stacked semiconductor die, providing alignment references and electrical connection pathways. The intermediary structure absorbs some alignment tolerances and provides a robust framework that maintains electrical connectivity even with minor variations in stacking precision.
4Productivity
If the package structure is made compact to improve density, then the surface area is reduced, but heat dissipation becomes more challenging
Solution Approach 1:
The patent implements local quality variations by providing enhanced thermal management pathways at critical locations within the compact package. Heat sink structures, thermal vias, and thermally conductive materials are strategically placed near high-power density regions of the stacked die. The package substrate incorporates thermal management features in specific areas rather than uniformly throughout, allowing effective heat dissipation from hot spots while maintaining overall package compactness.
Data Source
AI summary
Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method includes encapsulating a device stack within a molded panel having a frontside and a backside. The device stack contains an upper semiconductor die and an interconnect buffer layer, which is formed over the upper semiconductor die and which is covered by the frontside of the molded panel. Material is removed from the frontside the molded panel to expose the interconnect buffer layer therethrough. One or more frontside redistribution layers are produced over the frontside of the molded panel and electrically coupled to the upper semiconductor die through the interconnect buffer layer. The molded panel is then singulated to yield a microelectronic package including a molded package body containing the device stack.