Stacked Microelectronic Packages via Wafer-Level Bonding
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Solution Overview
Problem
There is a need for improved wafer-scale and stacked wafer-scale microelectronic packages that are both reliable and economical to manufacture, as existing methods face challenges in efficiently utilizing space and reducing costs while maintaining performance standards.
Innovation Solution
The method involves creating a stacked unit by attaching two wafers with microelectronic elements using an adhesive layer or alternative bonding methods, followed by dicing to form individual units, and then forming trace bridges for electrical connectivity, allowing for efficient stacking and connection to substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple microelectronic chips are stacked within a package to save space, then the package occupies less surface area on the substrate, but the manufacturing complexity and reliability challenges increase
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional stacking by forming vertical vias through intermediate substrates to connect die in multiple layers. This dimensional change allows multiple chips to occupy vertical space rather than horizontal space, reducing the package footprint while managing complexity through systematic via formation and alignment processes.
2Ease of manufacture
If wafer level packaging is used to divide packaging costs among various die, then the cost differential between die and component is reduced, but additional fabrication process steps are required
Solution Approach 1:
The patent combines multiple packaging operations into a single wafer-level process. Multiple die on a wafer are packaged simultaneously through collective substrate attachment, via formation, and dicing operations. This merging of operations distributes packaging costs across all die on the wafer while the systematic process integration manages the complexity of additional fabrication steps.
3Area of stationary object
If conventional stacked packages are used to reduce PCB area utilization, then space is saved, but the manufacturing reliability and electrical connectivity between stacked units become challenging
Solution Approach 1:
The patent performs preliminary alignment and attachment of multiple wafers to substrate assemblies before dicing. Vias are formed and conductive material is deposited while the wafer is still in its stacked configuration, ensuring proper electrical connectivity is established before the final singulation step. This preliminary action ensures reliability is built into the structure before separation into individual packages.
Solution Approach 2:
The patent introduces intermediate substrates as mediators between stacked die layers. These substrates provide mechanical support and electrical interconnection pathways through formed vias, facilitating reliable electrical connectivity between stacked units while enabling the compact PCB area utilization achieved through vertical stacking.
4Length of stationary object
If tapes such as copper-on-polyimide are used as substrates to provide thinner packages, then package thickness is reduced, but the manufacturing cost increases significantly
Solution Approach 1:
The patent changes the substrate parameter from thin flexible tapes to thicker rigid or semi-rigid substrates that can be processed at the wafer level. This parameter change enables the use of cost-effective manufacturing processes and materials while still achieving thin overall package thickness through optimized stacking and via formation, thereby reducing manufacturing cost while maintaining the thickness benefit.
Data Source
Figure 1A~2
Figure 3~4
Figure 5A~6
AI summary
A microelectronic assembly (34) that includes a first microelectronic element (12) having a first rear surface (16). The assembly further includes a second microelectronic element (12a) having a second rear surface (16a). The second microelectronic element (12a) is attached to the first microelectronic element (12) so as to form a stacked package (34). The first rear surface (16) of the first microelectronic element (12) faces toward the second rear surface (16a) of the second microelectronic element (12a).