Stacked MIM Capacitor Structure Without High-AR Trench Etching

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Solution Overview

Problem

The complexity of IC manufacturing is increased by the need for high aspect ratio (AR) trench etch processes and high uniformity depositions for electrodes and insulators in MIM capacitors, along with the requirement of additional cap supporters and through vias, which raises costs and occupies excessive space.

Innovation Solution

A vertically stacked multi-layer MIM capacitor design with interleaved electrodes that eliminates the need for high AR trench etch processes and high uniformity depositions, reducing manufacturing costs and space by increasing the overlap area between electrodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high aspect ratio trench etch processes are used to increase capacitance, then capacitance is improved, but manufacturing complexity and cost increase

Engineering Contradiction:
ImprovecapacitanceVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent transitions from planar capacitor structures to vertically stacked multi-layer structures. By stacking multiple capacitor layers in the vertical dimension, the capacitance is increased without requiring high aspect ratio trenches. The interleaved electrode arrangement in multiple layers provides the needed capacitance while using standard etch processes, thus resolving the contradiction between capacitance improvement and manufacturing complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent employs nested structures where multiple capacitor layers are stacked within a compact vertical space. Each capacitor layer contains electrodes and dielectric materials nested within one another, with interleaved electrodes from adjacent layers. This nesting approach increases capacitance density without requiring excessive vertical height or complex high aspect ratio etching.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Manufacturing precision

If high uniformity depositions are used for electrodes and insulators, then manufacturing precision is improved, but manufacturing cost increases

Engineering Contradiction:
Improvedeposition uniformityVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The capacitor structure is segmented into multiple discrete layers, each formed by separate deposition processes. This segmentation allows standard deposition techniques to be used on each layer without requiring ultra-high uniformity across a single thick structure. The interleaved electrode design further segments the capacitance contribution, allowing each layer to be manufactured with conventional precision standards.

Inventive Principle:
Principle #1Segmentation

3Stability of the object's composition

If additional cap supporters and through vias are added, then structural stability is improved, but space occupation and manufacturing complexity increase

Engineering Contradiction:
Improvestructural stabilityVSAvoidspace occupation
Core Design Contradiction:
Stability of the object's compositionVSArea of stationary object

Solution Approach 1:

The patent merges the electrode structures of adjacent capacitor layers by using interleaved electrodes that extend through the dielectric material. This merging eliminates the need for separate cap supporters and through vias that would otherwise be required to provide structural stability and electrical connections. The interleaved electrodes serve both as functional capacitor elements and as structural support, reducing space occupation and manufacturing complexity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12432941B2Capacitor and method for forming the same
Publication Date: 2025.09.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12432941B2 patent drawing
  • US12432941B2 patent drawing
  • US12432941B2 patent drawing

AI summary

The method includes forming a sacrificial multi-layer stack including alternating first sacrificial layers and second sacrificial layers stacked in a vertical direction on a substrate; removing the first sacrificial layers to form first spaces each interposing two of the second sacrificial layers; depositing a first dielectric layer and a first electrode material in the first spaces; removing the second sacrificial layers to form second spaces each interposing two portions of the first electrode material; depositing a second dielectric layer and a second electrode material in the second spaces.