Stacked MIM Capacitor Layout for High-Density GaN Integration
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Solution Overview
Problem
The integration of capacitors in gallium nitride (GaN) power devices is limited by parasitic inductance, leading to oscillation and potential damage due to spike voltages, and the existing single die process platform restricts capacitor integration density due to the large area occupied by dielectric layers.
Innovation Solution
The integration of multiple capacitors in parallel within a single integrated device, utilizing a metal-insulator-metal (MIM) configuration with a gate metal layer, dielectric layers, and metal layers, along with a two-dimensional electron gas, to increase capacitor capacity and density, while connecting these capacitors through conductor structures to enhance voltage withstand and integration efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single die process platform is used to integrate capacitors, then the device structure is simplified, but the capacitor integration density is limited due to the large area occupied by dielectric layers
Solution Approach 1:
The patent transitions from planar capacitor integration to three-dimensional stacked capacitor integration. Multiple capacitor structures are stacked vertically along the thickness direction, utilizing the Z-dimension to increase integration density without expanding chip area. The dielectric layers and electrode plates are arranged in multiple levels, transforming a two-dimensional layout problem into a three-dimensional structure.
Solution Approach 2:
The patent implements nested capacitor structures where capacitor units are embedded within each other in the vertical direction. The first capacitor, second capacitor, and third capacitor are stacked and interconnected through conductor structures that pass through multiple dielectric layers, creating a nested configuration that maximizes space utilization and integration density.
2Ease of manufacture
If conventional capacitor integration methods are used, then the manufacturing process is simple, but the capacitor capacity is insufficient to handle spike voltages
Solution Approach 1:
The patent combines multiple capacitor structures in parallel to achieve the desired total capacitance value. The first capacitor, second capacitor, and third capacitor are connected through conductor structures to form a parallel configuration, where the total capacitance is the sum of individual capacitances. This merging approach increases the overall capacitor capacity to handle spike voltages while maintaining compatibility with conventional manufacturing processes.
Solution Approach 2:
The patent changes the capacitance parameter by integrating multiple capacitor units with different capacitance values. The first capacitor has a first capacitance value, the second capacitor has a second capacitance value, and their combination provides a total capacitance that meets the requirements for voltage spike suppression. This parameter optimization enables the device to withstand higher voltages without compromising manufacturing simplicity.
3Quantity of substance
If the dielectric layer thickness is increased to achieve required capacitance, then the capacitor capacity increases, but the chip area occupied by the dielectric layer increases
Solution Approach 1:
The patent resolves the area-capacitance trade-off by moving from horizontal expansion to vertical stacking. Instead of increasing dielectric layer thickness to boost capacitance (which would consume more chip area), the patent stacks multiple capacitor units in the thickness direction, utilizing the vertical dimension to achieve higher total capacitance without increasing the horizontal chip footprint.
Solution Approach 2:
The patent segments the total capacitance requirement into multiple smaller capacitor units. Rather than using a single large capacitor that would occupy significant chip area, the total capacitance is divided into first capacitor, second capacitor, and third capacitor, each with smaller individual areas. These segmented units are stacked vertically, achieving the required total capacitance while minimizing the horizontal chip area occupation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves capacitor integration density and voltage withstand performance, allowing the integrated device to operate at higher voltages with reduced size and increased reliability, addressing the limitations of existing GaN power devices.
Implementation Method 1
an aluminum gallium nitride layer disposed below the P-type conductive layer, where a two-dimensional electron gas is included below the aluminum gallium nitride layer
Data Source
AI summary
An integrated device, a semiconductor device, and an integrated device manufacturing method are provided, to improve capacitor integration density of the integrated device. The integrated device includes: A first dielectric layer is disposed on a first metal layer; the first metal layer, the first dielectric layer, and a gate metal layer on the first dielectric layer form a first capacitor; the gate metal layer, a second dielectric layer on the gate metal layer, and a second metal layer on the second dielectric layer form a second capacitor; and the first metal layer is connected to the second metal layer through a first conductor structure, so that the first capacitor and the second capacitor are connected in parallel.