Stacked MIM Capacitor Layout for GaN Gate Voltage Stability
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Solution Overview
Problem
The integration of capacitors in gallium nitride power devices is limited by the chip area due to the thickness of dielectric layers, leading to potential overvoltage damage and incorrect device turn-on, especially in fast turn-on processes.
Innovation Solution
An integrated device structure is developed with multiple metal-insulator-metal (MIM) capacitors connected in parallel or series, utilizing a gallium nitride layer, aluminum gallium nitride layer, and two-dimensional electron gas to increase capacitor density and withstand higher voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a metal layer is used to form an electrode plate of a capacitor on a single die process platform, then the capacitor can be integrated, but the integration is limited by chip area due to the thickness of dielectric layers
Solution Approach 1:
The patent transitions from planar capacitor integration to three-dimensional vertical integration by stacking multiple dielectric layers and metal electrode plates in the vertical dimension. This allows capacitors to be integrated without occupying additional chip area, effectively resolving the contradiction between capacitor integration density and chip area utilization.
Solution Approach 2:
The patent implements a stacked capacitor structure where multiple dielectric layers and metal plates are nested vertically, with each capacitor unit containing conductive layers embedded within dielectric layers. This nested configuration enables high-density capacitor integration while maintaining compact chip footprint.
2Speed
If the gate of the device is driven in a fast turn-on process, then the turn-on speed is improved, but oscillation occurs in the driving waveform due to parasitic inductance, causing overvoltage damage or incorrect turn-on
Solution Approach 1:
The patent introduces an integrated capacitor as an intermediary element connected to the gate terminal, which acts as a local energy reservoir and voltage stabilizer. This capacitor suppresses voltage oscillations caused by parasitic inductance during fast turn-on, preventing overvoltage damage while maintaining high-speed operation.
Solution Approach 2:
The capacitor is positioned close to the gate terminal to provide beforehand cushioning against voltage oscillations. By placing the capacitor in proximity to the gate, the patent creates a local energy reservoir that compensates for voltage fluctuations before they can cause damage, enabling reliable fast turn-on operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances capacitor integration density, improves voltage withstand performance, and allows the device to operate at higher voltages with increased reliability and efficiency.
Implementation Method 1
utilizing a gallium nitride layer, aluminum gallium nitride layer, and two-dimensional electron gas to increase capacitor density and withstand higher voltages
Data Source
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AI summary
An integrated device, a semiconductor device, and an integrated device manufacturing method are provided, to improve capacitor integration density of the integrated device. The integrated device in embodiments of this application includes: A first dielectric layer is disposed on a first metal layer; the first metal layer, the first dielectric layer, and a gate metal layer on the first dielectric layer form a first capacitor; the gate metal layer, a second dielectric layer on the gate metal layer, and a second metal layer on the second dielectric layer form a second capacitor; and the first metal layer is connected to the second metal layer through a first conductor structure, so that the first capacitor and the second capacitor are connected in parallel.