Stacked MIM Capacitor Structure for Low Parasitic Capacitance
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Solution Overview
Problem
Semiconductor devices based on Bipolar, BiCMOS and CMOS techniques face issues with low voltage linearity and high parasitic capacitance in general MOS capacitors.
Innovation Solution
The use of a metal-insulator-metal capacitor design with stacked electrodes and dielectric layers, featuring a staircase-shaped edge region and controlled interior angles, to enhance reliability and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a general MOS capacitor is used, then the device can be manufactured with standard processes, but voltage linearity is low due to space charge region and parasitic capacitance is high
Solution Approach 1:
The capacitor is segmented into multiple electrodes (first electrode, second electrode, third electrode) with intermediate dielectric layers. This segmentation eliminates the space charge region present in conventional MOS capacitors, achieving high voltage linearity while reducing parasitic capacitance through the metal-insulator-metal structure.
Solution Approach 2:
The capacitor uses composite material structure with metal electrodes (first electrode, second electrode, third electrode) and dielectric materials (first dielectric layer, second dielectric layer). This composite MIM structure provides both high voltage linearity and low parasitic capacitance, resolving the contradiction between reliability and harmful factors.
2Area of stationary object
If electrodes are extended to surrounding regions, then coverage and capacitance are improved, but manufacturing complexity and potential damage increase
Solution Approach 1:
The electrodes extend not only in the planar direction but also in the vertical dimension, with each electrode covering both the upper surface and side surfaces of the underlying electrode. This three-dimensional configuration increases effective coverage area while maintaining manageable manufacturing complexity through conformal deposition processes.
Solution Approach 2:
The capacitor structure follows a nested configuration where the second electrode covers the first electrode, and the third electrode covers the second electrode, with each layer extending to surrounding regions. This nested design maximizes coverage area while simplifying manufacturing by using sequential deposition steps.
3Reliability
If dielectric layers cover upper surfaces and side surfaces, then electrode protection and insulation are improved, but manufacturing precision requirements increase
Solution Approach 1:
The dielectric layers are formed as thin conformal films that wrap around the electrodes, covering both upper surfaces and side surfaces. This thin film approach provides effective protection and insulation while reducing manufacturing precision requirements compared to thick rigid layers, as conformal deposition can achieve uniform thickness on complex geometries.
Data Source
AI summary
A metal-insulator-metal capacitor includes a first electrode disposed in a first region of an upper surface of a substrate, a second electrode covering the first electrode and extending to a second region surrounding an outer periphery of the first region, a third electrode covering the second electrode and extending to a third region surrounding an outer periphery of the second region, a first dielectric layer disposed between the first electrode and the second electrode to cover an upper surface and a side surface of the first electrode and extending to the second region, and a second dielectric layer disposed between the second electrode and the third electrode to cover an upper surface and a side surface of the second electrode and extending to the third region and in contact with the first dielectric layer.