Stacked MIM Capacitor Structure for High Density
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Solution Overview
Problem
Conventional metal-insulator-metal (MIM) capacitors face challenges in achieving high capacitance without increasing chip size or compromising reliability, as methods to enhance capacitance, such as using high dielectric constants or larger dielectric areas, often lead to increased production costs and reduced reliability.
Innovation Solution
The solution involves a capacitive device structure with multiple capacitors connected in parallel using vias that contact conductive layers and pass through dielectric films, allowing for increased capacitance without requiring larger chip sizes or reducing reliability, by utilizing a stacked configuration of wiring, dielectric, and conductive layers with specific via connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the dielectric area is increased to achieve higher capacitance, then the capacitance increases, but the chip size increases and production costs increase
Solution Approach 1:
The patent transitions from a planar capacitor structure to a three-dimensional stacked structure with multiple capacitors arranged vertically. This dimensional change allows capacitance to be increased by adding layers in the vertical direction rather than expanding the horizontal chip area, thereby resolving the contradiction between capacitance and chip size.
Solution Approach 2:
The patent divides a single large capacitor into multiple smaller capacitors arranged in parallel across different layers. Each capacitor contributes to the total capacitance, and their combined effect achieves high capacitance without requiring a large individual dielectric area, thus reducing chip size.
2Quantity of substance
If the dielectric is made thinner to increase capacitance, then the capacitance increases, but the reliability of the MIM capacitor decreases
Solution Approach 1:
Instead of increasing capacitance by reducing dielectric thickness in a single layer, the patent uses multiple layers stacked vertically. Each layer can maintain a sufficient dielectric thickness for reliability while the cumulative capacitance of all layers provides the desired high capacitance value.
3Quantity of substance
If the dielectric constant is increased to achieve higher capacitance, then the capacitance increases, but production costs increase
Solution Approach 1:
The patent achieves high capacitance through increased dielectric volume via vertical stacking rather than by using materials with higher dielectric constants. This approach allows the use of standard, cost-effective dielectric materials while still achieving high capacitance through the multi-layer configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a capacitive device with enhanced capacitance compared to conventional devices without the need for increased chip size or reliability degradation, maintaining performance while optimizing manufacturing costs.
Implementation Method 1
a first capacitor including a first wiring layer, a first dielectric film, and a first conductive layer
Implementation Method 2
an MIM capacitor can be embodied to have a low series resistance and a high Q (Quality Factor) value
Data Source
AI summary
A capacitive device includes a first capacitor including a first wiring layer, a first dielectric film, a first conductive layer, a first insulating layer on the first capacitor, a second capacitor on the first insulating layer including a second conductive layer, a second dielectric film, and a third conductive layer, a second insulating layer on the second capacitor, a second wiring layer on the second insulating layer including first and second connection wires, a first via connecting the first wiring layer to the second conductive layer, a second via connecting the third conductive layer to the second wiring layer, a third via connecting the first connection wire to the first conductive layer, and a fourth via connecting the second connection wire to the first wiring layer.