Stacked MIM Capacitors With Floating Plates for High-Voltage ICs
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Solution Overview
Problem
Conventional metal-insulator-metal (MIM) capacitors face challenges in supporting high voltage applications while maintaining capacitance per area, as they either require large surface areas or thick dielectric layers, which reduce capacitive density and increase production costs.
Innovation Solution
The use of multiple floating metal layers with minimum dielectric thickness and via connections between them forms high-voltage-tolerant MIM capacitors, increasing capacitance without increasing surface area, and allowing for configurable voltage tolerance across the integrated circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MIM capacitors use thick dielectric layers to support high voltage applications, then voltage tolerance is improved, but capacitance per area decreases
Solution Approach 1:
The patent divides a single thick-dielectric capacitor into multiple stacked capacitor units, each with thin dielectric layers. These units are connected in parallel through conductive vias to achieve high voltage tolerance while maintaining high capacitance per area. The segmentation allows each unit to operate at lower voltage individually while the parallel combination provides overall high voltage capability.
Solution Approach 2:
The patent transitions from a planar capacitor structure to a three-dimensional stacked structure. By stacking multiple capacitor units vertically and connecting them through vias, the design utilizes the vertical dimension to increase total capacitance without increasing surface area, thereby maintaining high capacitance per area while achieving voltage tolerance.
2Reliability
If conventional MIM capacitors increase surface area to support high voltage applications, then voltage tolerance is improved, but device area increases
Solution Approach 1:
The patent segments the capacitor into multiple stacked units that share common bottom and top electrodes. This segmentation allows the capacitor to achieve high voltage tolerance through the stacking configuration rather than requiring increased surface area, as each unit contributes to the total capacitance in parallel.
Solution Approach 2:
The patent exploits the vertical dimension by stacking multiple capacitor units one on top of another. This three-dimensional arrangement increases the effective capacitor area without increasing the footprint on the substrate, thereby maintaining compact device area while achieving high voltage tolerance.
3Quantity of substance
If multiple floating metal layers with via connections are used to form high-voltage-tolerant MIM capacitors, then capacitance per area increases, but device complexity increases
Solution Approach 1:
The patent merges multiple capacitor units into a single integrated structure by sharing common bottom and top electrodes. The floating metal layers are connected through vias to form a unified parallel capacitor configuration, which increases capacitance per area while managing complexity through electrode sharing and integrated via connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves high capacitive density and reliability under high voltage stress without increasing surface area or manufacturing costs, providing efficient capacitance and voltage tolerance in integrated circuits.
Implementation Method 1
A MIM capacitor is formed with two parallel metal plates separated by a dielectric layer
Implementation Method 2
The material selection for the dielectric layer is limited as many of the materials used for the dielectric layer are able to diffuse with the metal layers
Data Source
AI summary
A system and method for fabricating on-die metal-insulator-metal capacitors capable of supporting relatively high voltage applications and increasing capacitance per area are described. In various implementations, an integrated circuit includes multiple metal-insulator-metal (MIM) capacitors between a first signal net and a second signal net. The integrated circuit includes multiple intermediate floating metal layers (or metal plates) formed between two signal nets. The floating plates have no connection to any power supply reference voltage level used by the integrated circuit. At least one pair of floating metal layers have a via connection between them to reduce the overall insulating thickness of the resulting MIM capacitor.