Stacked MIM MOS Capacitor LDO Compensation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Low drop-out (LDO) voltage regulators face challenges in achieving good transient response over all process corners due to the large area requirements of metal-insulator-metal (MIM) compensation capacitors, while indirect feedback through metal-oxide-semiconductor (MOS) capacitors results in inadequate performance.
Innovation Solution
A stacked MIM/MOS compensation capacitor structure is employed, providing direct and indirect feedback to achieve a good settling response over all corners with a significant reduction in integrated circuit area, combining the benefits of both types of capacitors in a single horizontal area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a direct compensation circuit with a MIM capacitor is used, then the transient response is good, but the integrated circuit area is large
Solution Approach 1:
The patent implements a stacked capacitor structure where a MIM capacitor and a MOS capacitor are vertically stacked and share the same horizontal area. The MIM capacitor is formed in upper metal layers while the MOS capacitor is formed in lower layers, allowing both capacitors to occupy the same footprint on the substrate. This nesting approach enables the circuit to achieve good transient response through the MIM capacitor while minimizing the overall integrated circuit area by utilizing the vertical dimension.
Solution Approach 2:
The patent transitions from a planar layout to a three-dimensional stacked structure. By forming capacitors in multiple vertical layers rather than placing them side-by-side in the same plane, the design utilizes the vertical dimension to reduce the horizontal footprint. The stacked capacitor structure allows compensation capacitors to be distributed across different metal layers, achieving area reduction while maintaining the required capacitance values for proper transient response.
2Area of stationary object
If an indirect compensation circuit with a MOS capacitor is used, then the integrated circuit area is reduced, but the transient response is inadequate
Solution Approach 1:
The patent combines both direct and indirect compensation circuits into a single unified structure. The stacked capacitor configuration integrates a MIM capacitor (providing direct compensation) and a MOS capacitor (providing indirect compensation) in close proximity, allowing both compensation mechanisms to work simultaneously. This merging enables the circuit to achieve good transient response across all process corners while maintaining reduced area compared to using only a MIM capacitor.
Solution Approach 2:
The patent employs a composite compensation structure using two different capacitor technologies (MIM and MOS) with complementary characteristics. The MIM capacitor provides stable, voltage-independent capacitance for direct compensation, while the MOS capacitor provides voltage-dependent characteristics for indirect compensation. This composite approach leverages the strengths of both capacitor types to achieve superior transient response across varying operating conditions while minimizing area.
Data Source
AI summary
A low drop-out (LDO) voltage regulator employs combined compensation methods for reduced capacitor area. Frequency compensation internal to a LDO voltage regulator is accomplished by introducing a metal-insulator-metal (MIM) compensation capacitor in series with a compensation resistor between an input to a second stage of the LDO voltage regulator and a regulator output. This achieves a good settling response over a wide range of load conditions at the expense of relatively large capacitor area. Alternatively, a metal-oxide semiconductor (MOS) compensation capacitor may be coupled between an intermediate node of a cascode circuit in a first stage of the LDO voltage regulator and the regulator output. This requires less capacitor area but exhibits instability at some corners. In combination, a good settling response over all corners may be achieved with stacked MIM/MOS capacitors occupying significantly less area than the MIM capacitor of the first method alone.