Stacked MIM and MOS Capacitors for Boosting Circuit Area Reduction
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Solution Overview
Problem
Conventional boosting circuits with charge pumps in semiconductor devices require large layout surface areas due to the size of boosting capacitors, which increases with higher output voltages, posing a challenge in reducing the overall circuit layout size as integration scales increase.
Innovation Solution
The semiconductor device employs a boosting circuit configuration where MIM capacitors are used in initial stages and MOS capacitors in subsequent stages, with these capacitors stacked vertically to minimize layout surface area, allowing for efficient voltage boosting while reducing the overall circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the output voltage from the boosting circuit is increased, then the voltage boosting capability is improved, but the layout surface area occupied by the boosting capacitor is further increased
Solution Approach 1:
The patent transitions from planar capacitor arrangement to three-dimensional stacking, where multiple capacitors are arranged vertically across different wiring layers. This dimensional change allows the boosting circuit to achieve higher output voltages without proportionally increasing the layout surface area, as capacitors utilize the vertical space above the semiconductor substrate rather than occupying additional horizontal area.
Solution Approach 2:
The patent implements a nested structure where capacitors are stacked within the vertical space above the semiconductor substrate, with each capacitor positioned in different wiring layers. This nesting approach allows multiple capacitors to occupy the same horizontal footprint while being separated vertically, thereby increasing voltage boosting capability without linearly increasing the layout surface area.
2Power
If the capacitance value of the boosting capacitor is increased, then the voltage boosting performance is improved, but the layout surface area is increased
Solution Approach 1:
The patent arranges multiple capacitors in the vertical dimension across different wiring layers (first, second, and third wiring layers) rather than spreading them out horizontally. This allows the total capacitance value to be increased by stacking capacitors vertically, maintaining high voltage boosting performance while minimizing the horizontal layout surface area occupied by the capacitor array.
Solution Approach 2:
The patent divides the total capacitance requirement into multiple smaller capacitors distributed across different wiring layers. Instead of using one large capacitor that would occupy significant horizontal area, the total capacitance is segmented into C1, C2, C3, and C4 positioned in different vertical layers, achieving the required capacitance value through vertical distribution rather than horizontal expansion.
Data Source
AI summary
A semiconductor device including: a semiconductor substrate; at least one circuit block provided on a main surface of the semiconductor substrate and having a predetermined function; a wiring layer including plural metal layers that connect the circuit block; and plural capacitors including a first capacitor connected to the circuit block and that uses the plurality of metal layers, and a second capacitor that uses an active area disposed within the main surface of the semiconductor substrate, wherein at least one of the first capacitor and at least one of the second capacitor are stacked in a stacking direction of layers of the semiconductor.