Stacked Electronic Module Layout for Lower PCB Footprint
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Solution Overview
Problem
The increasing number of electronic devices in smaller electronic modules poses challenges in reducing parasitic inductance and PCB footprint.
Innovation Solution
A stacking structure is implemented in the electronic module, featuring a first circuit board over a first electronic device with a second circuit board underneath, connected by conductors and flexible circuit boards, and power pins with a metal layer to reduce parasitic inductance and PCB footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of electronic devices in an electronic module is increased, then the functionality and performance of the module is improved, but the parasitic inductance and PCB footprint increase
Solution Approach 1:
The patent transitions from a traditional planar PCB layout to a three-dimensional stacking structure. Circuit boards are arranged in multiple layers (first circuit board, second circuit board, third circuit board) stacked vertically, with conductors connecting corresponding positions across layers. This vertical arrangement reduces the horizontal footprint while maintaining electrical connectivity and functionality.
Solution Approach 2:
The patent implements a nested configuration where electronic devices and circuit boards are stacked within a compact vertical space. The first electronic device is positioned between the first and second circuit boards, while the second electronic device is positioned between the second and third circuit boards, creating a nested arrangement that maximizes space utilization.
2Adaptability or versatility
If the number of electronic devices in an electronic module is increased, then the functionality and performance of the module is improved, but the parasitic inductance increases
Solution Approach 1:
By stacking circuit boards vertically and connecting them through conductors at corresponding positions, the patent creates short current loops in the vertical dimension. This reduces the area enclosed by current paths, thereby minimizing parasitic inductance while accommodating multiple electronic devices.
Solution Approach 2:
The patent divides the electronic module into multiple stacked layers with dedicated circuit boards and electronic devices in each layer. This segmentation allows for optimized current paths within each layer and reduces the overall loop area, thereby reducing parasitic inductance.
3Area of stationary object
If a stacking structure is implemented to reduce PCB footprint, then the area occupied is reduced, but the device complexity increases
Solution Approach 1:
The patent uses vertical stacking to reduce horizontal footprint, accepting increased structural complexity as a trade-off. Multiple circuit boards are arranged in layers with conductors connecting corresponding positions, creating a three-dimensional configuration that compresses the module in the horizontal plane.
Data Source
AI summary
An electronic module, comprising: a first electronic device, a first circuit board disposed over the first top surface, and a second circuit board disposed under the bottom surface of the body of the first electronic device, wherein a plurality of conductors are disposed over a first lateral surface for electrically connecting the first circuit board and the second circuit board, wherein a plurality of electrodes of the electronic module are disposed on a bottom surface of the second circuit board.