Stacked Semiconductor Module Layout for Wire Interference Isolation

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Solution Overview

Problem

In semiconductor packages where multiple semiconductor modules are mounted close together, wires from one module can interfere with adjacent modules, leading to short circuits due to interference or misalignment during assembly.

Innovation Solution

The semiconductor device incorporates an adhesive layer between vertically stacked semiconductor chips in the second module, allowing at least part of the connecting wires from the first module to be embedded within this layer, preventing interference and short circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If semiconductor modules are mounted close together to reduce device size, then the overall device size is reduced, but wires from one module may interfere with adjacent modules causing short circuits

Engineering Contradiction:
Improvedevice sizeVSAvoidshort circuit risk
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent introduces a resin layer as an intermediary substance between the wire and the second semiconductor module. This resin layer physically separates and insulates the wire from the adjacent module components, preventing potential short circuits while allowing the modules to be mounted in close proximity. The resin layer acts as a mediator that enables close spacing without compromising electrical isolation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent utilizes the vertical dimension by having the wire extend in a direction substantially perpendicular to the mounting surface and embed it within the resin layer. This three-dimensional arrangement allows wires to be routed vertically rather than horizontally across the module surface, reducing interference with adjacent modules and enabling closer horizontal spacing of semiconductor modules.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If wires are extended to connect semiconductor chips to the wiring board, then electrical connectivity is achieved, but the wires may interfere with adjacent semiconductor modules

Engineering Contradiction:
Improveelectrical connectivityVSAvoidwire interference
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent changes the wire routing from a horizontal planar arrangement to a vertical three-dimensional arrangement. The wire extends in a direction substantially perpendicular to the mounting surface, allowing it to connect the semiconductor chip to the wiring board through the resin layer without horizontally traversing across the module surface where it could interfere with adjacent modules.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The resin layer serves as an intermediary medium that the wire passes through. This embedding of the wire within the resin layer provides physical support and electrical insulation, allowing the wire to maintain its connectivity function while being isolated from adjacent semiconductor module components that could cause short circuits.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design prevents short circuits and allows for closer placement of semiconductor modules, reducing the overall size of the semiconductor device while maintaining electrical connectivity.

Implementation Method 1

The second semiconductor module includes an adhesive layer between an N-th second semiconductor chip and an (N+1)th second semiconductor chip from a lowermost layer

Methodology Applied
Scientific EffectAdhesive bonding: Adhesive

Data Source

PatentUS20260082590A1Semiconductor device and method of manufacturing semiconductor device
Publication Date: 2026.03.19 KIOXIA CORP
  • US20260082590A1 patent drawing
  • US20260082590A1 patent drawing
  • US20260082590A1 patent drawing

AI summary

According to one embodiment, a semiconductor device includes a wiring board, a first semiconductor module that includes one or more first semiconductor chips staked together, a wire that connects one of the one or more first semiconductor chips to the wiring board, and a second semiconductor module that is arranged adjacent to the first semiconductor module and includes second semiconductor chips stacked together. At least part of the wire is in contact with an adhesive layer between an N-th second semiconductor chip and an (N+1)th second semiconductor chip from a lowermost layer among the second semiconductor chips.