Stacked MoM Capacitors Using Front- and Back-Side Metallization
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Solution Overview
Problem
Current IC manufacturing processes face challenges in providing sufficient area for passive devices like MoM capacitors due to the reduction in die area, leading to increased demand for signal routing and limited space for capacitance density.
Innovation Solution
The integration of stacked MoM capacitors in both front and back side metallization layers of a semiconductor die, where the capacitors are formed in interdigitated conductive finger structures, allowing for increased capacitance density while conserving area for signal routing by utilizing both front and back side interconnect structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MoM capacitors are formed in front side metallization layers to increase capacitance density, then capacitance density is improved, but area available for signal routing is reduced
Solution Approach 1:
The patent utilizes the third dimension (vertical stacking) by forming capacitors in both front side and back side metallization layers. This dimensional transition allows capacitance to be increased without consuming additional planar area, as capacitors are stacked vertically rather than placed side-by-side. The back side metallization layers provide an additional layer for capacitor formation, effectively doubling the capacitance density while preserving front side area for signal routing.
2Area of moving object
If die area is reduced to meet miniaturization demands, then device size is improved, but area for passive devices like capacitors is reduced
Solution Approach 1:
By transitioning from planar capacitor placement to vertical stacking across front and back sides, the patent achieves higher capacitance density within a reduced die area. The stacked configuration allows multiple capacitors to occupy the same footprint area, effectively increasing the quantity of capacitance without proportionally increasing the die area.
Solution Approach 2:
The patent combines the back side metallization layers, which would otherwise be unused or underutilized, with the front side metallization layers to form a integrated stacked capacitor structure. This merging of front and back side resources maximizes the use of available space within the reduced die area.
3Area of stationary object
If back side metallization layers are used for power distribution network, then area for signal routing is improved, but capacitance density is reduced
Solution Approach 1:
The back side metallization layers are designed to serve multiple functions simultaneously: they provide power distribution network connectivity while also hosting MoM capacitor structures. This multi-functionality allows the same physical infrastructure to fulfill both power delivery and energy storage roles, maintaining capacitance density while preserving front side area for signal routing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Maintains or increases capacitance density in the die while providing sufficient area for signal routing, and reduces coupling resistance and inductance by locating the back side MoM capacitor close to the power distribution network, improving decoupling capacitance and reducing IR drop.
Implementation Method 1
Metal lines formed in the metallization layers of the interconnect can also be used to form passive devices, such as capacitors (e.g., metal-oxide-metal (MoM) capacitors). As an example, the structure of a MoM capacitor can provide a high capacitance in a reduced area of the die to provide a high capacitance density in the die.
Data Source
AI summary
Stacked metal-oxide-metal (MoM) capacitor(s) in front side and back side metallization layers of a semiconductor die, and related fabrication methods. The stacked MoM capacitor includes a first, front side, MoM capacitor formed on the front side of the semiconductor layer of a die and in front side metallization layers in a front side interconnect structure. The stacked MoM capacitor also includes a second, back side MoM capacitor formed on the back side of the semiconductor layer in back side metallization layers in a back side interconnect structure. The front side and back side MoM capacitors are coupled to each other through a conducting structure in a second, vertical direction between the front side and back side interconnect structures to form the stacked MoM capacitor. In this manner, capacitance density in the die can be maintained or increase while providing sufficient area in the front side metallization layers for signal routing.