Stacked MOS Capacitor Structure for High Density Integration
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Solution Overview
Problem
MOS capacitors in integrated circuits occupy significant silicon substrate area, leading to large device size and low capacitance density, which is a challenge for miniaturization and increased performance in circuit applications.
Innovation Solution
A semiconductor device with a capacitive structure that includes a well region, buried insulator layer, and a dual gate field effect transistor configuration, where the well region and gate layer are electrically coupled, and the source and drain regions are of the same conductivity type, forming a higher density MOS capacitance without increasing substrate area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MOS capacitors are used in integrated circuits, then capacitance function is achieved, but substrate area consumption increases
Solution Approach 1:
The patent implements a stacked capacitor structure where a first capacitor is formed in the first semiconductor layer and a second capacitor is formed in the second semiconductor layer directly above it. This nesting approach allows two capacitive elements to occupy the same lateral footprint, effectively doubling the capacitance density without increasing substrate area consumption.
Solution Approach 2:
The invention transitions from planar capacitor布局 to three-dimensional stacked architecture by utilizing the vertical dimension. Multiple semiconductor layers are stacked above the buried insulator, with capacitors formed in each layer, thereby increasing capacitance along the vertical axis rather than expanding laterally.
2Quantity of substance
If conventional MOS capacitor structure is used, then simple fabrication is maintained, but capacitance density remains low
Solution Approach 1:
The capacitor structure is segmented into multiple independent capacitive elements stacked vertically. Each capacitor consists of its own semiconductor layer, insulator layer, and electrode structures, allowing independent formation and optimization of each capacitive element while achieving high total capacitance density.
Solution Approach 2:
The patent employs composite material structures including silicon layers, silicon oxide insulators, and silicon nitride layers arranged in a stacked configuration. This composite approach enables simultaneous achievement of high capacitance density and compatibility with standard semiconductor fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a higher capacitance density and reduces substrate area usage, enabling smaller integrated circuits with improved performance in applications like voltage doubler charge pump circuitry and RC-delay/trigger circuitry.
Implementation Method 1
a capacitive structure, wherein the capacitive structure may include the well region, at least one contact to the well region, at least a portion of the buried insulator layer over the well region, at least a portion of the second semiconductor layer
Data Source
AI summary
A semiconductor device may be provided, including a substrate which includes a first semiconductor layer having a well region arranged within the first semiconductor layer, a buried insulator layer arranged over the first semiconductor layer, and a second semiconductor layer arranged over the buried insulator layer. The semiconductor device may include a capacitive structure including: the well region, at least one contact to the well region, at least a portion of the buried insulator layer over the well region, at least a portion of the second semiconductor layer, a source region and a drain region arranged over the second semiconductor layer, a gate dielectric layer arranged over the second semiconductor layer and arranged laterally between the source region and the drain region, and a gate layer arranged over the gate dielectric layer. The well region, the source region, and the drain region may have the same conductivity type.