Stacked MOS ESD Clamp for High Voltage CMOS Interfaces
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Solution Overview
Problem
Conventional ESD protection circuits in CMOS technology are inadequate for high voltage interfaces, such as the 19v DC supply required by low noise block controllers, as they exceed the typical breakdown limits and face start-up issues due to complexity, and integrating voltage regulation onto the controller is desirable to minimize system costs.
Innovation Solution
A CMOS ESD circuit comprising a stack of MOS devices with resistors, an inverter device, and a time lag circuit that provides current clamping during ESD events, capable of handling DC voltage levels greater than conventional breakdown limits, using a resistor ladder and capacitors to manage voltage and prevent leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection circuits are used, then they can protect circuits up to 7.5v DC voltage, but they cannot handle high voltage interfaces exceeding 7.5v such as 19v DC supply
Solution Approach 1:
The ESD protection circuit is segmented into multiple series-connected MOS devices (first MOS device, second MOS device, third MOS device) that can each withstand a portion of the high voltage. This segmentation allows the circuit to handle voltages exceeding conventional limits by distributing the voltage stress across multiple devices, with each device operating within its safe breakdown voltage range.
2Reliability
If high voltage interface circuit is used to regulate voltage down to 3-5 volts, then voltage regulation is achieved, but system cost increases due to separate high voltage process manufacturing
Solution Approach 1:
The invention merges the ESD protection function and voltage regulation function into a single integrated circuit implemented in standard CMOS process. The stacked MOS devices with appropriate biasing and control circuits provide both high voltage tolerance and voltage regulation capabilities, eliminating the need for separate high voltage interface circuits manufactured in bipolar high voltage process, thereby reducing system cost while maintaining manufacturing compatibility.
3Reliability
If conventional ESD protection circuits handling up to 7.5v are used, then they work reliably at low voltage, but they face inherent start-up issues when adapted for high voltage applications
Solution Approach 1:
The circuit employs preliminary action through startup control mechanisms that properly initialize the stacked MOS devices before normal operation. The control circuits establish appropriate bias conditions and ensure proper turn-on sequences for the series-connected devices, preventing start-up issues that would arise from simply adapting low-voltage circuits to high voltage applications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively handles high DC voltages up to 21 volts, ensuring no leakage current during steady state and providing a safe ground return path during ESD events, thus protecting semiconductor structures from voltage breakdown.
Implementation Method 1
each MOS device in the stack having a gate-to-source voltage that is less than a turn-on threshold voltage of the MOS devices, thereby ensuring that no leakage current flows through the stack of MOS devices during steady state
Implementation Method 2
a plurality of capacitors pulling the voltage to each gate of the MOS devices in the stack to the supply voltage upon the inverter device turning off
Implementation Method 3
a time lag circuit that turns the inverter device on and off
Data Source
AI summary
An ESD circuit includes a plurality of MOS devices arranged in a stack, wherein each of the MOS devices comprises a source, a drain, and a gate; a voltage source inputting a supply voltage to the stack of MOS devices; a first plurality of resistors dividing the supply voltage to each source and each drain of the MOS devices in the stack; a second plurality of resistors biasing the supply voltage to each gate of the MOS devices in the stack; an inverter device operatively connected to the second plurality of resistors; a time lag circuit that turns the inverter device on and off; and a plurality of capacitors pulling the voltage to each gate of the MOS devices in the stack to the supply voltage upon the inverter device turning off.