Stacked MOS MOM Capacitor Architecture for Linearity
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Solution Overview
Problem
Stacked MOS/MOM capacitors used in high-density circuit applications exhibit non-linearity, which can lead to the need for additional MOM capacitance to achieve better linearity, increasing circuit area and complexity.
Innovation Solution
The implementation of a stacked capacitor architecture that combines MOS and MOM capacitances in a back-to-back configuration with biasing to operate in a linear region, allowing for improved linearity and reduced circuit area by using MOS capacitances alone or in conjunction with MOM capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If MOS capacitors are used to achieve area efficiency, then area is reduced, but linearity deteriorates due to capacitance variation with voltage
Solution Approach 1:
The patent combines MOS capacitors and MOM capacitors into a stacked capacitor architecture where the two capacitor types are vertically integrated. The MOS capacitor provides area efficiency while the MOM capacitor compensates for non-linearity, achieving both compact size and improved linearity through their synergistic combination.
Solution Approach 2:
The stacked capacitor uses a composite structure combining different capacitor technologies (MOS and MOM) with complementary characteristics. The MOS portion provides high density while the MOM portion provides linearity, creating a composite capacitive element that leverages the strengths of both types.
2Area of stationary object
If stackcap architecture is used to achieve high density, then area is reduced, but linearity deteriorates requiring additional MOM capacitance
Solution Approach 1:
The patent implements dynamic biasing of the MOS capacitor within the stackcap to optimize its operating point and minimize non-linear effects. By dynamically adjusting the bias voltage, the MOS capacitor can operate in a more linear region, reducing the need for additional MOM capacitance compensation.
Solution Approach 2:
The patent changes the operating parameters of the MOS capacitor through biasing techniques to improve its linearity. By adjusting the bias voltage and operating point, the capacitance-voltage characteristics are optimized to reduce non-linear variations, thereby improving overall linearity without sacrificing area efficiency.
3Reliability
If additional MOM capacitance is added to improve linearity, then linearity is improved, but device complexity increases
Solution Approach 1:
The patent transitions from a planar layout to a vertical three-dimensional stacked architecture. By stacking the MOS and MOM capacitors vertically, the design achieves improved linearity through the complementary characteristics of the two capacitor types without increasing the horizontal footprint or overall device complexity.
Data Source
AI summary
A device includes a first stacked capacitor comprising a first MOS capacitance and a first MOM capacitance, the first MOS capacitance coupled to a first node, the first node configured to receive a first bias voltage, and a second stacked capacitor comprising a second MOS capacitance and a second MOM capacitance, the second MOS capacitance coupled to the first node.