Stacked MOSFET Channel and Backside Contact for Reliability
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Solution Overview
Problem
The scale-down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties and reliability, necessitating improved electrical characteristics and reliability in semiconductor devices.
Innovation Solution
A semiconductor device design featuring stacked semiconductor patterns with varying doping concentrations and backside contacts to enhance electrical connectivity and reliability, including a substrate with source/drain patterns, interlayer insulating layers, and power delivery network layers, with specific doping profiles and contact structures to optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for smaller pattern sizes, then device size is reduced, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional stacked channel structures (multiple semiconductor patterns stacked vertically). This dimensional change allows the device to maintain electrical performance by providing multiple conduction paths while reducing the lateral footprint, thus achieving scale-down without operational deterioration
Solution Approach 2:
The channel region is segmented into multiple discrete semiconductor patterns (first, second, third semiconductor patterns) stacked vertically. Each pattern acts as an independent conduction path, and the collective effect maintains or enhances operational properties while reducing overall device area compared to a single large planar channel
2Reliability
If source/drain patterns are heavily doped to improve electrical conductivity, then electrical characteristics improve, but stress-related damage increases
Solution Approach 1:
The patent applies different doping concentrations to different regions of the source/drain patterns. The first pattern has a first doping concentration that decreases vertically, while the second pattern has a second doping concentration. This local differentiation allows optimization of electrical conductivity in critical regions while reducing stress-related damage in other regions by avoiding uniform heavy doping throughout
3Ease of manufacture
If backside contacts are designed with constant width to simplify manufacturing, then ease of manufacture improves, but electrical connectivity and stress distribution are suboptimal
Solution Approach 1:
The backside contact is designed with varying width along its vertical extent - wider at the bottom portion and narrower at the top portion. This non-uniform geometry optimizes electrical connectivity by providing larger contact area at the substrate interface while reducing stress concentration at upper regions, and still maintains manufacturing feasibility through a single continuous structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves electrical characteristics and reliability by optimizing doping concentrations and contact structures, enhancing the semiconductor device's operational performance and reducing stress-related damage.
Implementation Method 1
The first pattern has a first doping concentration, and the first doping concentration decreases as a vertical distance from the substrate in an upward direction increases
Implementation Method 2
a backside contact penetrating the substrate and in contact with the first pattern
Implementation Method 3
the channel pattern comprising a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern, the first, second, and third semiconductor patterns being stacked to be spaced apart from each other
Data Source
AI summary
A semiconductor device may include a substrate, source/drain patterns on the substrate, the source/drain patterns comprising a first pattern and a second pattern, the first and second patterns being spaced apart from each other, a channel pattern between the first pattern and the second pattern, the channel pattern comprising a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern, the first, second, and third semiconductor patterns being stacked to be spaced apart from each other, an interlayer insulating layer on the source/drain patterns, an active contact penetrating the interlayer insulating layer and in contact with the second pattern, and a backside contact penetrating the substrate and in contact with the first pattern.