Stacked MOSFET Interconnect Barrier for Diffusion Reliability
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOSFETs) in semiconductor devices leads to deterioration in operational properties, necessitating improved electrical characteristics and reliability.
Innovation Solution
A semiconductor device design featuring vertically stacked semiconductor patterns with a gate electrode and metal interconnection structures, including a diffusion prevention pattern made of ruthenium oxide to prevent diffusion and enhance electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOSFETs are scaled down to meet increasing demand for small pattern size, then device size is reduced, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar MOSFET structure to vertically stacked semiconductor patterns (multi-layer channel structure), moving the channel formation into the third dimension. This allows continued scaling of device footprint while maintaining operational properties through increased vertical channel area.
Solution Approach 2:
The patent employs composite material structures including semiconductor patterns with specific crystal orientations, gate electrodes with multiple material layers, and diffusion prevention patterns with ruthenium oxide. These composite structures maintain electrical characteristics while enabling smaller device dimensions.
2Reliability
If diffusion prevention pattern level is lowered to prevent diffusion, then diffusion barrier is improved, but electrical connectivity may be affected
Solution Approach 1:
The patent introduces a selection barrier pattern as an intermediary layer between the diffusion prevention pattern and the interconnection pattern. This mediator enables the diffusion prevention pattern to be positioned at a lower level while maintaining electrical connectivity through the selection barrier, which provides both diffusion blocking and conductive pathways.
Solution Approach 2:
The patent divides the barrier structure into multiple functional segments: diffusion prevention pattern for blocking atomic diffusion, selection barrier pattern for selective diffusion control and electrical connection, and interconnection pattern for signal transmission. This segmentation allows each layer to optimize its specific function without compromising others.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves electrical characteristics and reliability by preventing diffusion and ensuring effective electrical connectivity, thus addressing the challenges posed by the scaling down of MOSFETs.
Implementation Method 1
a diffusion prevention pattern between the first interconnection pattern and the second conductive via
Implementation Method 2
the diffusion prevention pattern may include ruthenium oxide
Data Source
AI summary
A semiconductor device may include a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including semiconductor patterns vertically stacked to be spaced apart from each other, a gate electrode on the plurality of semiconductor patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the gate contact, the first metal layer including a first conductive via and a first interconnection pattern on the first conductive via, a second metal layer on the first metal layer, the second metal layer including a second conductive via and a second interconnection pattern on the second conductive via, and a diffusion prevention pattern between the first interconnection pattern and the second conductive via. A level of a bottom surface of the diffusion prevention pattern may be lower than a level of the topmost surface of the first interconnection pattern.