3D Stacked MOSFET Channel Layout for Higher Logic Cell Density
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Solution Overview
Problem
As semiconductor devices are scaled down, the operating characteristics of MOSFETs deteriorate, leading to challenges in achieving superior performance and high integration while maintaining electrical properties.
Innovation Solution
A three-dimensional semiconductor device is designed with a substrate having multiple regions, each with specific active sections and channel patterns, including single height cells, double height cells, and active contacts, to enhance integration and electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MOSFET sizes are scaled down to increase integration, then device density increases, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertically stacked channel patterns (e.g., four channels stacked vertically per transistor). This dimensional change allows multiple channels to occupy the same footprint area, increasing effective channel width and drive current without increasing lateral device area, thereby maintaining electrical performance while achieving higher integration density.
Solution Approach 2:
The channel region is segmented into multiple discrete vertical channels (first through fourth channels) stacked at different heights. Each channel can be independently controlled by corresponding gate electrodes, allowing the transistor to function as multiple parallel channels. This segmentation increases the effective conducting area and improves current drive capability while maintaining compact footprint.
2Reliability
If channel widths are increased to improve electrical properties, then transistor performance improves, but device area increases
Solution Approach 1:
Instead of increasing channel width in the lateral plane, the patent extends the channel structure vertically by stacking multiple channels at different heights (lower and upper channels). This vertical extension increases the effective channel width without increasing the lateral footprint, allowing improved electrical properties within the same device area.
Solution Approach 2:
Multiple channel structures are nested vertically within the same lateral footprint. The first and second lower channels are positioned at a first height, while the third and fourth lower channels are positioned at a second height, creating a nested three-dimensional arrangement that maximizes space utilization and increases effective channel width without expanding device area.
3Quantity of substance
If multiple active sections are stacked vertically to increase integration, then device density increases, but manufacturing complexity increases
Solution Approach 1:
The vertical stack is segmented into distinct height levels (first height and second height), with each level containing specific channel and source/drain patterns. This segmentation allows for systematic fabrication processes where each layer can be formed and aligned independently, managing the complexity of vertical stacking through structured layering.
Solution Approach 2:
The gate electrode structure serves multiple functions: it controls multiple vertically stacked channels simultaneously and acts as a common control element for the entire stack. This multi-functionality reduces the number of separate components needed and simplifies the overall device architecture despite the vertical complexity.
Data Source
AI summary
Disclosed is a three-dimensional semiconductor device comprising a substrate including first and second regions, a first active section on the first region and including a first lower channel pattern and a first lower source/drain pattern, a second active section on the first active section and including a first upper channel pattern and a first upper source/drain pattern, a third active section on the second region and including a second lower channel pattern and a second lower source/drain pattern, a fourth active section on the third active section and including a second upper channel pattern and a second upper source/drain pattern, and a gate electrode on the first and second lower channel patterns and the first and second upper channel patterns. A first width in a first direction of the first lower channel pattern is greater than a second width in the first direction of the second lower channel pattern.