Stacked MOSFET Contact Interface Layers for Electric Characteristics
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Solution Overview
Problem
There is a need for semiconductor devices with improved reliability, performance, and multi-functionality to meet the increasing demands of the electronic industry, particularly in terms of complexity and integration density, which existing semiconductor devices have not adequately addressed.
Innovation Solution
A semiconductor device design featuring vertically-stacked semiconductor patterns with different conductivity type source/drain patterns, interface layers made of distinct metallic elements, and contact plugs that penetrate interlayer insulating layers, optimizing the structure to enhance electric characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different metallic elements are used in interface layers for PMOSFET and NMOSFET regions, then electric characteristics are improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by using different metallic elements (e.g., titanium for PMOSFET, tungsten for NMOSFET) in interface layers at different regions of the semiconductor device. This allows optimization of electric characteristics for each transistor type (PMOSFET and NMOSFET) with conductivity types, while maintaining a systematic approach to the overall device structure.
2Quantity of substance
If vertically-stacked semiconductor patterns are used, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements vertically-stacked semiconductor patterns that extend in the vertical direction (third direction) perpendicular to the substrate surface. This three-dimensional stacking arrangement increases the number of semiconductor patterns and source/drain patterns within a given planar area, thereby improving integration density without requiring additional lateral space.
3Reliability
If contact plugs penetrate interlayer insulating layers to connect source/drain patterns, then electrical connectivity is improved, but device complexity increases
Solution Approach 1:
The patent uses contact plugs as intermediary elements that penetrate the interlayer insulating layer to establish electrical connections between the vertically-stacked semiconductor patterns and external circuitry. These contact plugs serve as mediators bridging different layers and conductivity types, enabling reliable electrical connectivity while maintaining a structured approach to interlayer communication.
Data Source
AI summary
A semiconductor device includes a first and second channel patterns on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including different metallic elements from each other, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom surface of a topmost one of the semiconductor patterns.