3D Stacked MOSFET Active Contact Layout for Reliable Scaling
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Solution Overview
Problem
As semiconductor devices are scaled down, the operating characteristics of MOSFETs deteriorate, leading to challenges in achieving superior performance and high integration while maintaining reliability.
Innovation Solution
A three-dimensional semiconductor device is fabricated with stacked active regions, including lower and upper channel patterns and source/drain patterns, along with a gate electrode structure and active contacts, to enhance reliability and integration by allowing vertical stacking of transistors and symmetrical active contacts that reduce manufacturing complexity and defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET sizes are scaled down to achieve high integration, then device density increases, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from two-dimensional planar MOSFETs to three-dimensional vertically-stacked MOSFETs. Multiple channel patterns (first lower channel pattern, second lower channel pattern, first upper channel pattern, second upper channel pattern) are stacked vertically to increase device density without further scaling lateral dimensions, thereby maintaining operating characteristics while achieving higher integration density.
Solution Approach 2:
The device is segmented into multiple discrete transistor units stacked vertically, with each unit having its own channel patterns and source/drain regions. This segmentation allows independent optimization of each transistor unit while achieving high overall integration through vertical stacking.
2Reliability
If asymmetric active contacts are used to connect stacked source/drain patterns, then electrical connection is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent employs asymmetric active contact structures where different contact patterns are used for different transistor types. First active contacts connect to first source/drain patterns (e.g., NMOS), while second active contacts connect to second source/drain patterns (e.g., PMOS). This asymmetry enables selective electrical connection to appropriate transistor terminals while simplifying the overall manufacturing by using standard photolithography patterning processes.
Solution Approach 2:
Different active contact structures are implemented in different local regions of the device. First active contacts with specific patterns are formed in regions corresponding to first transistor types, while second active contacts with different patterns are formed in regions corresponding to second transistor types, optimizing electrical connection for each transistor type locally.
Data Source
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AI summary
A three-dimensional semiconductor device comprises a first active region (AR1) on a substrate (100) and including a lower channel pattern (CH1) and a lower source/drain pattern (SD1) connected to the lower channel pattern, a second active region (AR2) stacked on the first active region and including an upper channel pattern (CH2) and an upper source/drain pattern (SD2) connected to the upper channel pattern, a gate electrode structure (GE) on the lower channel pattern and the upper channel pattern, a first active contact (AC1) electrically connected to the lower source/drain pattern, an upper separation structure (USS) between the first active contact and the upper source/drain pattern, a second active contact (AC2) electrically connected to the upper source/drain pattern, and a lower separation structure (LSS) between the second active contact and the lower source/drain pattern.