Stacked MOSFET Current Mirror Layout for Mismatch Reduction
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Solution Overview
Problem
Integrated circuit manufacturing in deep-submicron processes faces challenges in producing transistors and amplifiers due to process scaling, leading to current mismatch issues in current mirror circuits, as MOSFETs with long channel lengths are not feasible.
Innovation Solution
Stacking multiple transistors with short channel lengths to form equivalent transistors with long channel lengths, reducing current mismatch by connecting gates of transistors in series and using bias voltage to control them, and optimizing transistor arrangements for reduced area and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If MOSFETs with long channel lengths are used to reduce current mismatch, then current matching precision is improved, but device area increases and process scalability deteriorates
Solution Approach 1:
The patent divides a single long-channel MOSFET into multiple short-channel MOSFETs connected in series (stacked configuration). Each transistor in the stack has a short channel length suitable for deep-submicron processes, but their series connection creates an equivalent long-channel device that reduces current mismatch. This segmentation allows achieving precise current matching without requiring physically large long-channel transistors.
2Area of stationary object
If process scaling is advanced to reduce device size, then device area is reduced, but manufacturing precision deteriorates due to bottlenecks in deep-submicron processes
Solution Approach 1:
Instead of using a single transistor with scaled dimensions that suffers from manufacturing variability, the patent segments the current path into multiple series-connected transistors. Each transistor can be manufactured using standard deep-submicron processes with controlled dimensions, and their series connection achieves the equivalent electrical characteristics of a long-channel device, thereby maintaining manufacturing precision while enabling area reduction.
Solution Approach 2:
The patent changes the electrical parameters of the transistor stack by connecting multiple transistors in series, which transforms the equivalent channel length and current characteristics. This parameter transformation allows the circuit to achieve long-channel behavior (reduced current mismatch) while using short-channel transistors that are compatible with scaled manufacturing processes.
3Measurement precision
If multiple transistors are stacked in series to form equivalent long-channel transistors, then current mismatch is reduced, but device complexity increases
Solution Approach 1:
The patent merges multiple short-channel transistors into a unified stacked-gate structure where their gates are connected together and controlled by a single control signal. This merging approach simplifies the control architecture while achieving the current matching benefits of equivalent long-channel transistors. The combined structure behaves as a single device with improved current characteristics.
Solution Approach 2:
The stacked-gate transistor structure serves multiple functions: it provides current matching precision equivalent to long-channel devices, maintains compatibility with short-channel manufacturing processes, and can be controlled by a unified gate signal. This multi-functionality reduces the overall system complexity despite the increased number of transistor components.
Data Source
AI summary
An integrated circuit includes a first circuit with m first units coupled in parallel, any of the first units including one or more first transistors coupled in series, and a second circuit with n second units coupled in parallel, any of the second units including one or more second transistors coupled in series. A gate terminal of the first circuit is coupled to a gate terminal of the second circuit. M and n are different positive integers.