Stacked MOSFET Channel Structure With Gate Cuts for Low Resistance
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Solution Overview
Problem
The scale-down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improved electrical characteristics.
Innovation Solution
A semiconductor device design featuring stacked semiconductor patterns, gate cutting patterns, and spacer patterns with different materials, along with a gate electrode extension and interlayer connections, enhances the device's electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to reduce pattern size, then device density increases, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional stacked semiconductor patterns (e.g., nanosheet channels) that extend vertically. This dimensional change allows the channel to wrap around the gate electrode in multiple directions, increasing the effective channel area and improving gate control without increasing the lateral footprint, thereby maintaining small pattern size while improving operational properties through enhanced carrier transport and reduced short-channel effects
Solution Approach 2:
The channel pattern is configured to surround and wrap around the gate electrode in a nested arrangement, with the channel forming a three-dimensional structure that encloses the gate from multiple sides. This nesting geometry increases the gate-controlled channel area while maintaining compact lateral dimensions, resolving the contradiction between small device footprint and effective gate control for improved operational characteristics
2Reliability
If gate cutting patterns penetrate the gate electrode, then electrical resistance is reduced, but device complexity increases
Solution Approach 1:
The gate electrode is divided into multiple discrete gate segments by inserting conductive gate cutting patterns between them. This segmentation allows independent electrical control of different channel regions, enables lower resistance current paths through the gate structure, and facilitates advanced device configurations such as split-gate or multi-gate transistors, reducing overall electrical resistance while managing complexity through modular design
Solution Approach 2:
Conductive gate cutting patterns are introduced as intermediary elements between gate electrode segments. These cutting patterns serve multiple functions: they provide low-resistance electrical connections, act as additional control gates for the channel, and enable independent biasing of different regions. The intermediaries reduce overall device resistance while the modular segmented approach manages structural complexity
Data Source
AI summary
A semiconductor device may include a first active pattern on a substrate, a pair of first source/drain patterns on the first active pattern and a first channel pattern between the first source/drain patterns, the first channel pattern including first semiconductor patterns, which are spaced apart from each other in a stacked formation, a gate electrode on the first channel pattern, a first gate cutting pattern adjacent to the first channel pattern that penetrates the gate electrode, and a first spacer pattern between the first gate cutting pattern and the first channel pattern. The first spacer pattern may include a first remaining pattern adjacent to an outermost side surface of at least one of the first semiconductor patterns and a second remaining pattern on the first remaining pattern. The second remaining pattern may be spaced apart from the first gate cutting pattern.