3D Stacked MOSFET Gate Insulation for Scaled Device Reliability
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Solution Overview
Problem
The scale-down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improved electrical characteristics and fabrication methods.
Innovation Solution
A semiconductor device design featuring vertically stacked semiconductor patterns with a gate insulating layer of varying thicknesses and a gate electrode configuration that includes a gate insulating layer covering opposite side surfaces and top/bottom surfaces of semiconductor patterns, along with a method of fabricating this structure through etching and sacrificial layer removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If MOS-FETs are scaled down to reduce design rule, then device size is reduced, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structure to vertically stacked 3D channel structure. Multiple semiconductor patterns are stacked in the vertical direction (third direction) to form a three-dimensional channel, allowing the device to maintain electrical performance while reducing the lateral footprint on the substrate. This dimensional change enables continued scaling without proportionally degrading operational properties.
Solution Approach 2:
The gate insulating layer is designed with non-uniform thickness, having a first thickness in the first direction (lateral direction) and a second thickness in the second direction (vertical direction), where the first thickness is greater than the second thickness. This local variation in thickness optimizes the electrical characteristics by providing better insulation where needed while maintaining effective gate control, thus improving operational properties in the scaled-down device.
2Reliability
If gate insulating layer thickness is increased to improve insulation, then electrical isolation is enhanced, but device area increases
Solution Approach 1:
Instead of increasing the gate insulating layer thickness uniformly in all directions, the patent utilizes the vertical dimension by stacking multiple semiconductor patterns. The gate insulating layer is positioned between the gate electrode and the stacked semiconductor patterns, providing effective electrical isolation without requiring large lateral dimensions. This approach enhances electrical isolation while maintaining compact device area.
Solution Approach 2:
The gate insulating layer exhibits different thickness characteristics in different directions: a first thickness in the lateral direction (first direction) and a smaller second thickness in the vertical direction (second direction). This anisotropic thickness distribution provides enhanced electrical isolation in the lateral direction where it is most needed, while minimizing the vertical footprint, thus achieving good electrical isolation without proportionally increasing overall device area.
Data Source
AI summary
A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns and extending in a first direction, and a gate insulating layer between the semiconductor patterns and the gate electrode. A first semiconductor pattern of the semiconductor patterns includes opposite side surfaces in the first direction, and bottom and top surfaces. The gate insulating layer covers the opposite side surfaces, and the bottom and top surfaces and includes a first region on one of the opposite side surfaces of the first semiconductor pattern and a second region on one of the top or bottom surfaces of the first semiconductor pattern, and a thickness of the first region may be greater than a thickness of the second region.