Stacked NMOS/PMOS Gate Structure for Scaled MOSFET Isolation
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Solution Overview
Problem
The scale-down of MOSFETs in semiconductor devices leads to deteriorated operational properties, necessitating improvements in electric characteristics and reliability.
Innovation Solution
A semiconductor device design featuring a substrate with active regions and field regions, where channel patterns are vertically stacked and a gate electrode extends across the field region with a decreasing lower portion width from the substrate surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOSFETs are scaled down to reduce pattern size and layout footprint, then device integration density is improved, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertically stacked channel patterns. Multiple channel patterns are stacked in the vertical direction above the substrate, enabling increased device density without further lateral scaling. This dimensional change allows maintaining operational properties while reducing layout footprint.
Solution Approach 2:
The gate electrode is divided into multiple discrete gate electrodes, each controlling a separate channel pattern. The channel patterns themselves are segmented into multiple vertically stacked segments. This segmentation allows independent optimization of each channel and improves overall device performance while enabling higher integration density.
2Length of moving object
If gate electrode width is reduced for further scaling, then device size is reduced, but insulating properties between gate and source/drain deteriorate
Solution Approach 1:
A gate insulating layer is introduced as an intermediary between the gate electrode and the channel patterns. This insulating layer provides electrical isolation and prevents direct contact, ensuring proper insulating properties even as device dimensions are reduced. The gate insulating layer acts as a mediator that maintains electrical integrity during scaling.
Solution Approach 2:
The gate insulating layer is selectively positioned at critical interfaces where the gate electrode contacts or approaches the channel patterns. This local application of insulating material provides enhanced electrical isolation precisely where needed, maintaining insulating properties without requiring uniform increases in gate electrode width.
Data Source
AI summary
A semiconductor device may include a substrate including first and second active regions and a field region therebetween, first and second active patterns respectively provided on the first and second active regions, first and second source/drain patterns respectively provided on the first and second active patterns, a first channel pattern between the first source/drain patterns and a second channel pattern between the second source/drain patterns, and a gate electrode extended from the first channel pattern to the second channel pattern to cross the field region. Each of the first and second channel patterns may include semiconductor patterns, which are stacked to be spaced apart from each other. A width of a lower portion of the gate electrode on the field region may decrease with decreasing distance from a top surface of the substrate.