Stacked MOSFET Channel Structure With Nonuniform Gate Oxide
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Solution Overview
Problem
The scale-down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improved electrical characteristics.
Innovation Solution
A semiconductor device design featuring vertically stacked semiconductor patterns with a gate insulating layer of varying thicknesses and a gate electrode configuration that enhances electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If MOS-FETs are scaled down to reduce device size, then device integration density is improved, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertically stacked semiconductor patterns, enabling multiple channels to be stacked in the vertical direction. This dimensional change allows increased device density without further lateral scaling, thereby maintaining operational properties while reducing overall device footprint.
Solution Approach 2:
The gate insulating layer is designed with non-uniform thickness, featuring a first thickness in the horizontal direction and a second thickness in the vertical direction. This local quality variation optimizes electrical characteristics by providing different insulation properties at different locations, addressing operational challenges associated with scaled-down devices.
2Volume of moving object
If gate insulating layer thickness is reduced to enable further scaling, then device density is improved, but electrical characteristics deteriorate
Solution Approach 1:
The gate insulating layer exhibits different thicknesses in different directions: a first thickness in the horizontal direction and a second thickness in the vertical direction. This anisotropic thickness distribution allows optimized electrical characteristics while maintaining high device density, resolving the contradiction between scaling and electrical performance.
Solution Approach 2:
The gate insulating layer is formed as a composite structure with regions of varying thickness, combining the benefits of thin insulation for high density with thicker regions that maintain electrical characteristics. This composite approach enables simultaneous achievement of high device density and reliable electrical performance.
Data Source
AI summary
A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns and extending in a first direction, and a gate insulating layer between the semiconductor patterns and the gate electrode. A first semiconductor pattern of the semiconductor patterns includes opposite side surfaces in the first direction, and bottom and top surfaces. The gate insulating layer covers the opposite side surfaces, and the bottom and top surfaces and includes a first region on one of the opposite side surfaces of the first semiconductor pattern and a second region on one of the top or bottom surfaces of the first semiconductor pattern, and a thickness of the first region may be greater than a thickness of the second region.