Stacked MOSFET Gate Structure for Scaled Device Reliability
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Solution Overview
Problem
As semiconductor devices are scaled down, their operating characteristics deteriorate, leading to challenges in achieving superior performance and integration, particularly in maintaining reliable electrical properties.
Innovation Solution
A semiconductor device design featuring vertically stacked semiconductor patterns with specific source/drain and gate electrode configurations, including inner and outer electrodes, and a gate dielectric layer with an inverted T shape, along with a metal-semiconductor compound layer and active contacts, to enhance electrical connections and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET sizes are scaled down to increase integration, then device density increases, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertically stacked semiconductor patterns, enabling multiple channels to occupy a smaller footprint area while maintaining adequate channel dimensions for proper device operation
Solution Approach 2:
The gate electrode is divided into multiple segments (first gate electrode and second gate electrode) that can be independently controlled, allowing separate optimization of operating characteristics for different channel regions while maintaining high integration density
2Productivity
If vertically stacked semiconductor patterns are used, then device integration improves, but manufacturing complexity increases
Solution Approach 1:
The vertically stacked semiconductor patterns serve multiple functions simultaneously: they provide the channel structure, define active regions, and enable independent gate control, reducing the need for separate structural elements and simplifying the overall device architecture
Solution Approach 2:
The patent combines multiple functional elements into integrated structures, such as merging the channel and active region definitions into the vertically stacked semiconductor patterns, and integrating multiple gate controls into a unified vertical architecture
Data Source
AI summary
Disclosed is a semiconductor device comprising a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns spaced apart from and vertically stacked on each other, a source/drain pattern connected to the semiconductor patterns having a p-type, a gate electrode on the semiconductor patterns and including inner electrodes between neighboring semiconductor patterns and an outer electrode on an uppermost semiconductor pattern, and a gate dielectric layer between the gate electrode and the semiconductor patterns and including an inner gate dielectric layer adjacent to the inner electrode and an outer gate dielectric layer that extends from bottom to lateral surfaces of the outer electrode. The outer electrode and the outer gate dielectric layer have an inverted T shape.