Stacked MOSFET Channel Structure With Region-Specific High-k Thickness
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Solution Overview
Problem
The scaling down of MOSFETs in semiconductor devices leads to deteriorated operating characteristics, necessitating improved methods for manufacturing devices with superior performance and increased reliability.
Innovation Solution
A semiconductor device design featuring stacked semiconductor patterns with varying thicknesses and gate dielectric layers, including high-k dielectric materials, to enhance electrical properties and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET sizes are scaled down to increase device density, then device density increases, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertically stacked channel structures. Multiple semiconductor patterns are stacked vertically to form channel patterns, enabling increased device density without further lateral scaling. This vertical dimension expansion allows maintaining reliable operating characteristics while achieving higher device density.
Solution Approach 2:
The gate dielectric layer employs a composite structure combining a first dielectric material layer and a second dielectric material layer with different properties. The first layer provides interface quality and the second layer provides high-k dielectric properties, creating a composite material system that optimizes both electrical performance and reliability in the scaled device structure.
2Ease of manufacture
If uniform gate dielectric layers are used across different regions, then manufacturing is simplified, but electrical properties cannot be optimized for different device regions
Solution Approach 1:
The gate dielectric layer structure varies by region to optimize electrical properties for different device requirements. First and second dielectric material layers are selectively formed with different thicknesses and material compositions in different regions (e.g., trench isolation regions versus active device regions), allowing local optimization of electrical characteristics while maintaining a systematic fabrication approach.
Solution Approach 2:
The patent varies physical and chemical parameters of the gate dielectric layer including material composition, layer thickness, and dielectric constant across different device regions. These parameter changes enable optimization of electrical properties such as threshold voltage and leakage current for different functional requirements while using a unified multi-layer fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves electrical properties and reliability of semiconductor devices by optimizing the thickness and composition of semiconductor and gate dielectric layers, enhancing device performance.
Implementation Method 1
a first gate dielectric layer between the first channel pattern and the first gate electrode, and a second gate dielectric layer between the second channel pattern and the second gate electrode
Implementation Method 2
the first gate dielectric layer includes a first interface layer and a first high-k dielectric layer, wherein the second gate dielectric layer includes a second interface layer and a second high-k dielectric layer
Data Source
AI summary
A semiconductor device includes: a substrate including first and second regions, first and second active patterns in the first and second regions, respectively; first source/drain patterns and a first channel pattern including first semiconductor patterns; second source/drain patterns and a second channel pattern including second semiconductor patterns; first and second gate electrodes on the first and second channel patterns, respectively; and a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer includes a first interface layer between the first channel pattern and the first gate electrode, and a first high-k dielectric layer. The second gate dielectric layer includes a second interface layer and a second high-k dielectric layer between the second channel pattern and the second gate electrode. A thickness of the first high-k dielectric layer is greater than that of the second high-k dielectric layer.