Stacked Gate-All-Around MOSFET Gate Structure for Leakage Control
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Solution Overview
Problem
As semiconductor devices are scaled down, their operating characteristics deteriorate due to increased integration, leading to challenges in achieving superior performance and reliable electrical properties.
Innovation Solution
A semiconductor device design featuring vertically stacked semiconductor patterns with a gate electrode structure that includes inner and outer electrodes, a capping pattern, and a gate dielectric layer, which improves electrical properties and reliability by mitigating leakage currents and enabling self-aligned contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET sizes are scaled down to increase integration, then device density increases, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertically stacked semiconductor patterns, enabling multiple channels to be stacked in the vertical direction. This dimensional change allows increased device density without further lateral scaling, while maintaining adequate channel dimensions for proper electrical characteristics.
Solution Approach 2:
The gate electrode is divided into multiple inner electrodes positioned between individual semiconductor patterns, with each inner electrode providing independent gate control for its corresponding channel. This segmentation enables precise control of each stacked channel while maintaining overall device integration.
2Reliability
If outer electrode height is increased to improve gate control, then electrical properties improve, but leakage currents increase
Solution Approach 1:
The patent optimizes the outer electrode height parameter to be equal to or less than its width, creating a specific geometric ratio that balances gate control effectiveness with leakage current suppression. This parameter optimization resolves the trade-off between improved electrical properties and harmful leakage effects.
Solution Approach 2:
The gate dielectric layer extends laterally to cover the outer electrode surface, acting as an intermediary that prevents direct exposure of the outer electrode. This lateral extension provides additional insulation that suppresses leakage currents while maintaining the beneficial gate control from the elevated outer electrode structure.
3Ease of manufacture
If gate electrode structure is simplified for easier manufacture, then manufacturing precision decreases, but fabrication complexity reduces
Solution Approach 1:
The gate structure is designed to be self-aligned, where the gate dielectric layer automatically extends to cover the outer electrode during the deposition process. This self-alignment mechanism eliminates the need for additional alignment steps, maintaining high precision while simplifying the manufacturing process.
Data Source
AI summary
Disclosed is a semiconductor device comprising a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns that are vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns and including inner electrodes between neighboring semiconductor patterns and an outer electrode on an uppermost semiconductor pattern, and a capping pattern on a top surface of the outer electrode. A line-width of the outer electrode is a first width. The outer electrode has a first height. The first height is equal to or less than the first width.