Stacked MOSFET Channel Structure With Liner Layer for Etch Reliability
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improved reliability and electric characteristics to maintain performance.
Innovation Solution
A semiconductor device design featuring stacked semiconductor patterns with specific width configurations and a gate electrode structure, including a liner layer and remnant semiconductor patterns, to enhance channel stability and prevent etching errors during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for smaller pattern sizes, then device density and integration are improved, but operational properties and reliability deteriorate
Solution Approach 1:
The patent transitions from planar channel structures to vertically stacked semiconductor patterns, moving the channel conduction path into the vertical dimension. This allows the device to achieve higher effective channel area without increasing the lateral footprint, thereby maintaining device density while improving operational properties through better channel control and reduced short-channel effects
Solution Approach 2:
The channel region is divided into multiple discrete semiconductor patterns stacked vertically, with gate electrodes positioned between them. This segmentation allows independent control and optimization of each channel segment, improving overall device reliability and electrical characteristics while maintaining compact lateral dimensions
2Manufacturing precision
If etching processes are used to form channel patterns, then manufacturing precision can be achieved, but etching errors and failures may occur
Solution Approach 1:
A liner layer is introduced as an intermediary between the semiconductor patterns and the etching environment. This liner layer protects the semiconductor patterns from direct exposure to etchants, preventing etching errors and failures while allowing precise formation of channel patterns through controlled etching processes
Solution Approach 2:
The liner layer is deposited beforehand to cushion and protect the semiconductor patterns during subsequent etching operations. This preventive measure ensures manufacturing precision by preventing etching damage before it can occur, thereby improving process stability and reducing defects
Data Source
AI summary
A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.