Stacked MOSFET Transistor Cells for Longer-Channel Node Porting
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Solution Overview
Problem
Advanced semiconductor process nodes lack higher voltage devices and longer channel length transistors, making it difficult to port designs and achieve die shrinkage, as these devices are not available or easily implementable, and new transistor models are in flux, complicating circuit design and assessment.
Innovation Solution
The use of transistor cells with uniform or mixed channel lengths organized into multi-stage stacked gate configurations, which can replace higher voltage and longer channel length devices, allowing for die shrinkage and easier database porting between process nodes, and are integrated into design tools for improved design flow and circuit modeling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If newer process nodes are adopted to shrink die size, then die area and cost are reduced, but availability of higher voltage devices and longer channel transistors is lost
Solution Approach 1:
The patent divides a single long channel transistor into multiple shorter channel transistors connected in series (stacked configuration). Each transistor in the stack has a channel length suitable for the newer process node, while the series connection provides the equivalent electrical characteristics of a longer channel device, including higher drain-to-source resistance and improved current mismatch performance.
Solution Approach 2:
The patent changes the electrical parameters by connecting multiple transistors in series, which modifies the overall drain-to-source resistance and threshold voltage characteristics. This allows the circuit to achieve the electrical behavior of higher voltage and longer channel devices using only the transistor geometries available at the newer process node.
2Measurement precision
If longer channel transistors are used to improve current mismatch performance, then current mirror accuracy is improved, but die area increases
Solution Approach 1:
The patent segments a single long channel transistor into multiple shorter channel transistors connected in series. This segmentation achieves the current mismatch performance of a long channel device while using only the smaller transistor geometries available at the newer process node, thereby reducing the overall die area required.
Solution Approach 2:
The patent transitions from extending the channel length in one dimension to stacking multiple transistors vertically in series. This dimensional change allows achieving the electrical characteristics of a long channel device without proportionally increasing the lateral die area, as the series connection provides the equivalent resistance and current matching performance.
3Adaptability or versatility
If thicker oxide is implemented to achieve higher voltage devices, then higher voltage capability is obtained, but device size and complexity increase
Solution Approach 1:
The patent segments the voltage handling function across multiple transistors in series. Each transistor in the stack handles a portion of the total voltage, allowing the use of thinner oxide processes while achieving higher voltage capability through the series connection of multiple standard-voltage transistors.
Solution Approach 2:
The patent creates a universal building block (stacked transistor cell) that can be configured to achieve different voltage and resistance characteristics by varying the number of transistors in the stack. This multi-functional cell replaces the need for separate higher voltage device libraries, simplifying the design process and enabling portability across process nodes.
4Adaptability or versatility
If multiple transistors are used to replace longer channel devices, then higher voltage capability is achieved, but parasitic capacitance and device count increase
Solution Approach 1:
The patent merges multiple transistors into a single functional unit or cell with shared control structures. By combining the transistors in a stacked configuration with common source/drain regions and control logic, the patent reduces the overall parasitic capacitance compared to using separate discrete transistors, while maintaining the higher voltage capability through the series connection.
Data Source
AI summary
A device including at least one transistor cell including metal-oxide semiconductor field-effect transistors each having drain/source terminals and a channel length. The at least one transistor cell includes a first number of transistors of the metal-oxide semiconductor field-effect transistors connected in series, with one of the drain/source terminals of one of the first number of transistors connected to one of the drain/source terminals of another one of the first number of transistors and gates of the first number of transistors connected together. The at least one transistor cell configured to be used to provide a transistor having a longer channel length than the channel length of each of the metal-oxide semiconductor field-effect transistors.