3D Stacked MOSFET Layout With Offset Contacts for Dense Routing
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Solution Overview
Problem
The scaling down of MOSFETs in semiconductor devices leads to deteriorated operating characteristics, necessitating improved manufacturing methods for enhanced performance and device density.
Innovation Solution
A three-dimensional semiconductor device design featuring vertically stacked transistors with offset and insulated active contacts, allowing for increased device density and reliability, including a substrate with vertically spaced source/drain patterns and non-overlapping channel patterns, connected by gate electrodes and active contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MOSFET sizes are scaled down to increase device density, then device density is improved, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from two-dimensional planar MOSFETs to three-dimensional vertically-stacked MOSFETs. Multiple active regions (first active region, second active region, third active region) are stacked vertically above each other on the substrate, enabling increased device density without further scaling of individual transistor dimensions. This vertical stacking allows more transistors to be packed into the same footprint area while maintaining adequate channel dimensions for proper operation.
Solution Approach 2:
The device is segmented into multiple independent active regions (first, second, and third active regions) stacked vertically. Each active region contains its own channel pattern, source/drain patterns, and gate electrode, forming separate transistor units. This segmentation allows each transistor to maintain optimal dimensions for operation while the stacked arrangement increases overall device density.
2Quantity of substance
If vertically stacked transistors are implemented, then device density is improved, but contact routing complexity increases
Solution Approach 1:
The patent employs asymmetric offset positioning of active contacts relative to the vertically-stacked source/drain patterns. The first active contact is positioned offset from the first source/drain pattern, the second active contact is offset from the second source/drain pattern, and the third active contact is offset from the third source/drain pattern. This asymmetric offset arrangement simplifies contact routing by preventing direct vertical alignment that would require complex through-silicon vias, while still enabling electrical connection to each stacked transistor level.
Solution Approach 2:
Offset active contacts serve as intermediary connection elements between the vertically-stacked source/drain patterns and the external circuitry. By positioning contacts offset from direct vertical alignment, intermediate routing layers and via structures are simplified, acting as mediators that reduce the complexity of connecting multiple stacked transistor levels to external pins.
3Manufacturing precision
If active contacts are offset from source/drain patterns, then manufacturing precision is improved, but electrical connection reliability may worsen
Solution Approach 1:
The offset positioning of active contacts relative to source/drain patterns is predetermined in the design stage. The first active contact is positioned offset from the first source/drain pattern, the second active contact is offset from the second source/drain pattern, and the third active contact is offset from the third source/drain pattern. This preliminary offset arrangement simplifies the alignment process during manufacturing, as the offset positions are clearly defined and do not require precise direct alignment, thereby improving manufacturing precision while maintaining reliable electrical connections through controlled routing paths.
Data Source
AI summary
Disclosed are three-dimensional semiconductor devices and their fabrication methods. The 3D semiconductor device includes a first active region on a substrate and including a lower channel pattern and a lower source/drain pattern connected to the lower channel pattern, a second active region above the first active region and including an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern, at least one gate electrode on the lower and upper channel patterns, a first active contact electrically connected to the lower source/drain pattern, and a second active contact electrically connected to the upper source/drain pattern. A first central line of the lower source/drain pattern and a second central line of the upper source/drain pattern in a vertical direction are offset from each other in a first direction perpendicular to the vertical direction. The first active contact and the second active contact are spaced apart from each other in the first direction.