Stacked N-Type MOSFET Layout for Lower Switch Loss
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices using n-type power MOSFETs face challenges in reducing mounting and package area while improving performance due to high resistance components, leading to increased switch loss when used as switches.
Innovation Solution
A semiconductor device comprising two n-type MOSFETs with parasitic diodes, where the semiconductor chips are stacked with their back surfaces in contact via a conductive member, reducing horizontal resistance and allowing for separate optimization of each MOSFET's structure to minimize on-resistance and package area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If two n-type power MOSFETs are formed on the same semiconductor substrate (third case), then the mounting area and package area are reduced, but the resistance component between the two MOSFETs becomes large due to horizontal electrical connection via drift region, drain electrode, and lead frame
Solution Approach 1:
The patent transitions from horizontal electrical connection to vertical electrical connection by stacking semiconductor chips in the thickness direction. This dimensional change eliminates the need for horizontal current paths through drift regions and lead frames, significantly reducing resistance components while maintaining compact package area.
Solution Approach 2:
The patent divides the semiconductor device into separate semiconductor chips, each containing one n-type power MOSFET. These segmented chips are then stacked and bonded together, allowing independent optimization of each chip's internal structure while achieving low resistance through vertical connections.
2Reliability
If n-type power MOSFETs are connected in series on the same substrate, then the device can prevent reverse current flow, but the horizontal resistance increases making it difficult to reduce switch loss
Solution Approach 1:
The patent arranges the series-connected n-type power MOSFETs in the vertical direction through chip stacking, creating current paths that flow perpendicular to the substrate planes. This eliminates horizontal resistance components and minimizes switch loss while maintaining reverse current prevention capability.
Solution Approach 2:
The patent changes the geometric arrangement parameter from horizontal to vertical, and optimizes the electrical connection parameters by using direct chip-to-chip bonding with conductive members, thereby minimizing resistance and reducing energy loss.
Data Source
AI summary
A semiconductor device includes a first semiconductor chip including a first MOSFET of n-type and a first parasitic diode and a second semiconductor chip including a second MOSFET of n-type and a second parasitic diode. A first source electrode and a first gate wiring are formed on a first front surface of the first semiconductor chip, and a first drain electrode is formed on a first back surface of the first semiconductor chip. A second source electrode and a second gate wiring are formed on a second front surface of the second semiconductor chip, and a second drain electrode is formed on a second back surface of the second semiconductor chip. The first back surface and the second back surface are faced to each other such that the first drain electrode and the second drain electrode are in contact with each other via a conductive tape.