Stacked Channel MOSFET Source/Drain Structure to Reduce Voids
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices, particularly MOS field effect transistors, are scaled down, their operating characteristics deteriorate, leading to challenges in achieving superior performance and high integration reliability.
Innovation Solution
The semiconductor device design includes a substrate with vertically stacked semiconductor patterns, source/drain patterns with protrusions of varying widths, and a gate electrode structure that extends across multiple channel patterns, along with a metal-semiconductor compound layer and interlayer insulating layers to enhance reliability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of the MOS field effect transistor is reduced to achieve high integration, then device density increases, but operating characteristics deteriorate and reliability decreases
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertically stacked channel patterns, enabling multiple channels to occupy the same footprint area. This dimensional change allows higher integration density while maintaining sufficient channel dimensions for reliable transistor operation, effectively decoupling density improvements from characteristic degradation.
Solution Approach 2:
The channel region is divided into multiple discrete semiconductor patterns stacked vertically, with source/drain patterns segmented into multiple protrusions corresponding to each channel level. This segmentation allows independent optimization of each channel while achieving high overall integration, preventing the deterioration seen in uniformly scaled-down devices.
2Ease of manufacture
If conventional source/drain patterns are used in vertically stacked channel structures, then manufacturing is simpler, but voids and lattice defects form reducing reliability
Solution Approach 1:
The source/drain pattern is designed with non-uniform local characteristics, featuring multiple protrusions with different widths at different horizontal positions. Each protrusion width is locally optimized to match the corresponding semiconductor pattern dimensions, ensuring complete coverage and intimate contact at each interface while avoiding void formation and lattice defects.
Solution Approach 2:
The source/drain pattern is formed with pre-designed protrusions that anticipate and accommodate the vertical stacking geometry of the channel structures. This preliminary geometric configuration ensures proper alignment and contact before final assembly, preventing defects that would otherwise require complex post-processing corrections.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A semiconductor device includes a substrate (100) including a first active pattern (AP1), a first channel pattern (CH1) on the first active pattern, the first channel pattern including first, second, and third semiconductor patterns (SP1-SP3) spaced apart from one another and vertically stacked, a first source/drain pattern (SD1) connected to the first to third semiconductor patterns (SP1-SP3), and a gate electrode (GE) on the first to third semiconductor patterns. The first source/drain pattern (SD1) includes a first protrusion (PRP1) protruding toward the first semiconductor pattern (SP1), a second protrusion (PRP2) protruding toward the second semiconductor pattern (SP2), and a third protrusion (PRP3) protruding toward the third semiconductor pattern (SP3). The protrusion length of the second protrusion (PRP2) being larger than the protrusion length of the first protrusion (PRP1) and the protrusion length of the third protrusion (PRP3) being larger than the protrusion length of the second protrusion (PRP2). The sidewalls of the semiconductor patterns (SP1-SP3) interfacing with the protrusions may be angled {111} crystal planes (FA1, FA2).