Stacked Multi-Chip Packaging Structure for DC-DC Converters
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Solution Overview
Problem
Conventional DC-DC converters with high-side and low-side MOSFET chips and an IC controller co-packaged on the same plane require larger package sizes, leading to higher electrical and thermal resistance due to wire bonding, resulting in lower electrical efficiency.
Innovation Solution
The solution involves stacking HS MOSFET and LS MOSFET chips on separate paddles of a lead frame, with an IC controller connected via a metal clip, allowing for a compact packaging structure that reduces electrical and thermal resistance by minimizing wire bonding, and includes a plastic package body for encapsulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If high-side MOSFET chip, low-side MOSFET chip and IC controller chip are arranged side by side on the same plane surface, then the package structure is simple, but the package size becomes larger and electrical and thermal resistance increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration. Multiple chip layers (high-side MOSFET, low-side MOSFET, IC controller) are arranged vertically on separate lead frame paddles, utilizing the third dimension (height/stacking direction) to reduce the horizontal package footprint while maintaining all necessary electrical connections.
2Ease of manufacture
If chips are arranged side by side on the same plane, then wiring is simpler, but wire bonding length increases leading to higher electrical and thermal resistance
Solution Approach 1:
By stacking chips vertically across multiple layers, the patent significantly reduces the horizontal distance between components. This dimensional transition shortens wire bonding lengths and interconnect paths, thereby reducing electrical resistance and thermal resistance despite the increased structural complexity of multi-layer wiring.
3Volume of moving object
If chips are stacked on separate paddles, then package size is reduced, but the packaging structure becomes more complex
Solution Approach 1:
The lead frame is divided into multiple separate paddles (first paddle, second paddle, third paddle), with each paddle carrying specific chip layers. This segmentation allows independent placement and connection of different chip stacks, managing the complexity through modular organization while achieving compact three-dimensional packaging.
Data Source
AI summary
A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the metal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip.