Stacked Multi-Die IC Packaging Without Through-Silicon Vias
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Solution Overview
Problem
Integrated circuit (IC) packages with multiple dies face challenges in minimizing size and reducing fabrication costs while maintaining signal routing efficiency, as splitting circuit functionality into multiple dies increases package size and complexity.
Innovation Solution
The implementation of a multi-die IC package design where dies are stacked vertically in separate packages, utilizing vertical interconnects and optional interposer substrates to provide signal routing without the need for through-silicon vias, allowing for separate fabrication and testing of each die package, and incorporating thermally conductive materials for heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If circuit functionality is split into multiple dies, then fabrication cost and complexity are reduced, but package size increases due to additional I/O signal paths and substrate structures
Solution Approach 1:
The patent transitions from a planar arrangement of multiple dies to a three-dimensional stacked configuration. Multiple dies are vertically stacked and interconnected through through-silicon vias (TSVs), enabling signal routing in the vertical dimension rather than requiring extensive horizontal I/O paths. This dimensional change reduces the horizontal package footprint while maintaining the benefits of multiple separate dies for fabrication and testing.
2Area of stationary object
If multiple dies are stacked vertically to reduce package area, then connection density increases, but the number of I/O connections required for signal routing increases
Solution Approach 1:
The patent introduces through-silicon vias (TSVs) as intermediary vertical interconnect structures that penetrate through the die substrates. These TSVs serve as mediators for signal routing between stacked dies, eliminating the need for complex lateral I/O signal paths around the periphery of each die. The TSVs provide direct vertical signal pathways, reducing the number of required I/O connections while enabling high connection density in the vertical dimension.
3Productivity
If separate die packages are used to allow independent fabrication and testing, then yield increases and cost decreases, but package complexity and size increase
Solution Approach 1:
The patent divides the integrated circuit system into multiple independent die segments that can be separately fabricated, tested, and processed. Each die can be manufactured on separate wafers using optimized processes for its specific function, then individually tested before being stacked and interconnected. This segmentation enables independent fabrication and testing, improving yield and reducing costs while the final stacked assembly provides the complete system functionality.
4Productivity
If through-silicon vias are used to provide vertical interconnects, then connection density and signal routing efficiency improve, but fabrication complexity and cost increase
Solution Approach 1:
The through-silicon vias (TSVs) are formed as preliminary structures during the die fabrication process itself, before the dies are stacked and assembled. The TSVs are created by drilling and filling vias through the die substrates with conductive material, establishing vertical interconnect pathways in advance. This preliminary formation of TSVs integrates the vertical interconnect fabrication into the standard die manufacturing process, reducing the complexity and cost that would arise from adding TSV formation as a separate post-assembly step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces package size, lowers fabrication costs, and enhances connection density while maintaining efficient signal routing and thermal management, thereby addressing the challenges of increased complexity and size associated with multi-die configurations.
Implementation Method 1
incorporating thermally conductive materials for heat dissipation
Data Source
AI summary
Multiple (multi-) die integrated circuit (IC) packages for supporting higher connection density, and related fabrication methods. The multi-die IC package includes split dies that provided in respective die packages that are stacked on top of each other to conserve package area. To support signal routing, including through-package signal routing that extends through the die package, each die package includes vertical interconnects disposed adjacent to their respective dies and coupled to a respective package substrate (and interposer substrate if provided) in the package substrate. In this manner, as an example, through-silicon-vias (TSVs) are not required to be fabricated in the multi-die IC package that extend through the dies themselves to provide signal routing between the respective die packages. In another example, space created between adjacent interposer substrates of stacked die packages, as stood off from each other through the interconnect bumps, provides an area for heat dissipation.