Stacked Multi-Gate Contacts With Lateral Trimming for Void-Free Filling
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the difficulty in filling metal into source/drain contact openings due to the small space, leading to voids or gaps, which deteriorates device performance, especially as the geometry size decreases and functional density increases in integrated circuits.
Innovation Solution
An etching process is employed to laterally trim the source/drain epitaxial structure around the contact opening, increasing the space and allowing for voids-free metal filling by ensuring the silicide layer does not hinder subsequent metal deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency is improved and costs are lowered, but the space for metal filling in source/drain contact openings becomes insufficient leading to voids and gaps
Solution Approach 1:
The patent introduces a lateral trimming dimension to the contact opening structure. By laterally trimming the source/drain epitaxial structure, the opening width is increased in the lateral direction, providing sufficient space for metal filling while maintaining the scaled-down vertical geometry, thus resolving the contradiction between small geometry size and adequate filling space
Solution Approach 2:
The patent performs preliminary lateral trimming of the source/drain epitaxial structure before metal deposition. This preliminary action creates an enlarged opening that anticipates the subsequent metal filling step, ensuring that the metal can be deposited without forming voids or gaps, thereby guaranteeing manufacturing precision at scaled dimensions
2Quantity of substance
If source/drain contact opening size is reduced due to scaling, then device density increases, but metal filling becomes difficult resulting in voids and gaps that deteriorate device performance
Solution Approach 1:
The patent resolves the density-performance contradiction by modifying the contact opening in the lateral dimension through trimming of the epitaxial structure. This creates additional horizontal space for metal filling while maintaining the reduced vertical profile needed for high device density, ensuring both high density and void-free filling for reliable device performance
Solution Approach 2:
The patent applies local quality modification by selectively trimming the source/drain epitaxial structure only in the regions surrounding the contact openings. This localized modification provides enlarged filling space exactly where needed (at the contact openings) while preserving the scaled-down geometry elsewhere, thereby achieving both high device density and reliable metal filling
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves metal filling during semiconductor processing, enhancing device performance and reliability by eliminating voids and gaps, thus supporting the scaling down of integrated circuits.
Implementation Method 1
An etching process is employed to laterally trim the source/drain epitaxial structure around the contact opening
Implementation Method 2
allowing for voids-free metal filling by ensuring the silicide layer does not hinder subsequent metal deposition
Data Source
AI summary
Method to form low-contact-resistance contacts to source/drain features is provided. A method of the present disclosure includes receiving a workpiece including an opening that exposes a surface of an n-type source/drain feature and a surface of a p-type source/drain feature, lateral epitaxial structures etching on the n-type source/drain feature creating the offset from the sidewall of the dielectric layer, depositing a silicide layer and the offset between etched epitaxial structures and sidewall of the dielectric layer is eliminated. The lateral epitaxial structures etching includes a reactive-ion etching (RIE) process and an atomic layer etching (ALE) process.