Stacked Multi-Gate Contact Structure for Low Via Resistance
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Solution Overview
Problem
In the semiconductor industry, particularly in sub-10 nanometer technology process nodes, stacked device structures like complementary field effect transistors (C-FET) face challenges such as merge void issues during metal gap fill processes in high aspect ratio openings, leading to poor device performance due to early metal pinch-off and increased contact resistance.
Innovation Solution
The solution involves adopting metal liner deposition or nucleation promoter deposition after silicide formation to ensure consistent metal growth rates and applying plasma etching to break through the liner bottom portion, allowing the metal plug to contact the silicide layer, thereby reducing merge voids and contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If metal gap fill process is used in high aspect ratio openings, then device density is improved, but merge void issues occur leading to poor device performance
Solution Approach 1:
A silicide layer is deposited as an intermediary layer between the metal plug and the source/drain epitaxy structures. This silicide layer serves as a mediator that facilitates controlled metal deposition and prevents direct metal-metallization interface issues, thereby eliminating merge voids while maintaining high device density
Solution Approach 2:
The silicide layer is formed in advance before the metal gap fill process. This preliminary action prepares the surface for subsequent metal deposition, ensuring uniform metal growth and preventing pinch-off issues that would otherwise occur in high aspect ratio openings
2Device complexity
If metal plug is formed directly in high aspect ratio opening, then manufacturing process is simplified, but contact resistance increases due to early metal pinch-off
Solution Approach 1:
The silicide layer acts as an intermediary that enables reliable metal contact formation. By depositing silicide before metal, the process creates a graded interface that prevents early pinch-off and ensures low contact resistance, while the additional step is justified by the significant improvement in electrical connectivity
3Manufacturing precision
If liner is used to line the opening, then metal growth consistency is improved, but contact resistance increases due to liner bottom portion blocking metal-silicide contact
Solution Approach 1:
The liner material is selectively removed from the bottom portion of the opening through plasma etching. This extraction allows direct metal-silicide contact at the critical interface while preserving the liner's beneficial effects on metal growth consistency in the upper portions of the opening
Solution Approach 2:
The liner presence is made non-uniform: it is removed from the bottom portion where direct contact is needed, while remaining in the upper portions where it provides structural support and guides metal growth. This local differentiation optimizes both metal growth consistency and electrical contact quality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves device performance by eliminating merge voids and reducing contact resistance, ensuring consistent metal growth and enhanced electrical connectivity between the silicide layer and metal plug.
Implementation Method 1
metal liner deposition
Implementation Method 2
applying plasma etching to break through the liner bottom portion
Data Source
AI summary
A semiconductor device that has two transistors and a source/drain contact. The first transistor has a layer of semiconductor material that acts as a channel, a structure that serves as a gate and wraps around the semiconductor channel layer, and two epitaxy structures on either end of the semiconductor channel layer that function as the source and drain. The second transistor is situated above the first transistor and has similar components, including a semiconductor channel layer, gate structure, and source/drain epitaxy structures. The connection between the first and second source/drain epitaxy structures is made by a source/drain contact that passes through one of the second source/drain epitaxy structures. This contact is made up of a metal plug and a metal liner that lines the plug.