Stacked Multi-Gate Transistor Layout for Short-Channel Suppression
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing integration density and improving performance due to limitations in scaling and short channel effects in multi-gate transistors.
Innovation Solution
A semiconductor device with a stacked multi-gate transistor design featuring a substrate with active patterns, gate structures, cutting structures, and through-vias that enhance electrical connectivity and reduce short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistor scaling is implemented to increase integration density, then integration density is improved, but short channel effects worsen
Solution Approach 1:
The patent implements a three-dimensional channel structure by stacking multiple active patterns (first lower active pattern, first upper active pattern, second lower active pattern, second upper active pattern) vertically on the substrate. This multi-gate transistor configuration allows current control from multiple directions (top, bottom, sides) while maintaining larger effective channel dimensions, thereby improving integration density without suffering from severe short channel effects that plague planar scaled-down transistors.
2Reliability
If gate length is increased to suppress short channel effects, then short channel effect suppression is improved, but current control capability worsens
Solution Approach 1:
The patent transitions from planar gate control to three-dimensional multi-gate control by forming gates that wrap around stacked active patterns. This enables effective channel length control without increasing the physical gate length, maintaining high current control capability while suppressing short channel effects through the vertical stacking architecture.
Solution Approach 2:
The patent employs nested gate structures where outer gates (first gate structure, second gate structure) surround and control inner active patterns. This nested configuration allows multiple gating levels to work together, providing enhanced electrostatic control over the channel while maintaining compact dimensional footprint.
3Productivity
If stacked multi-gate transistor structure is implemented to improve integration density, then integration density is improved, but device complexity worsens
Solution Approach 1:
The patent divides the transistor structure into discrete, modular segments including separate lower and upper active patterns, individual gate structures (first gate structure, second gate structure), and distinct cutting structures. This segmentation allows each component to be independently formed and optimized through standard semiconductor manufacturing processes, reducing overall device complexity despite the three-dimensional stacked architecture.
Solution Approach 2:
The cutting structures serve multiple functions: they electrically isolate adjacent transistors, provide mechanical release layers for stress engineering, and define active region boundaries. This multi-functionality reduces the need for separate dedicated structures, thereby improving integration density without proportionally increasing device complexity.
Data Source
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AI summary
A semiconductor device including a stacked multi-gate transistor includes a substrate, a first active pattern including a first lower active pattern and a first upper active pattern, a second active pattern including a second lower active pattern and a second upper active pattern, a first gate structure, a second gate structure on the second active pattern, the first gate structure and the second gate structure are aligned, a cutting structure between the first active pattern and the second active pattern, the cutting structure separating the first gate structure and the second gate structure, a front wiring pattern that extends on an upper surface of the cutting structure, a first back wiring pattern, and a first through-via that extends into the substrate and the cutting structure, the first through-via electrically connects the front wiring pattern and the first back wiring pattern.