Stacked Multi-Gate Transistor Layout for Short-Channel Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in integrating stacked multi-gate transistors effectively, which hinders the enhancement of integration and performance due to issues like short channel effects and limited current control capabilities.
Innovation Solution
A semiconductor device design featuring a substrate with alternating layers of active patterns and gate structures, including a front and back wiring structure, which allows for the stacking of multi-gate transistors to enhance integration and performance by improving current control without increasing gate length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistors are stacked to increase integration density, then device density and performance are improved, but short channel effects and current control capabilities deteriorate
Solution Approach 1:
The patent transitions from planar transistor layouts to three-dimensional stacked multi-gate structures. Multiple gate electrodes are positioned at different vertical levels around the channel, enabling control from multiple dimensions. This spatial arrangement allows effective suppression of short channel effects while maintaining high integration density, as the gates can control the channel potential more uniformly without requiring increased gate length.
2Reliability
If gate length is increased to improve current control, then current control capability is enhanced, but device area and integration density worsen
Solution Approach 1:
The patent implements nested gate structures where multiple gate electrodes are positioned concentrically or in stacked layers around the channel. The gates are arranged in a compact configuration where inner gates control lower channel regions and outer gates control upper regions, or vice versa. This nesting allows effective current control without extending the lateral gate length, thereby maintaining small device footprint and high integration density.
3Productivity
If stacked multi-gate transistors are implemented, then integration density is improved, but manufacturing complexity worsens
Solution Approach 1:
The patent divides the transistor structure into segmented components: separate gate electrodes at different vertical levels, distinct source/drain regions for each gate level, and corresponding insulating layers. Each segment can be formed through dedicated processing steps, allowing independent optimization and control. This segmentation simplifies the manufacturing of complex stacked structures by breaking down the fabrication into manageable, repeatable units that can be systematically assembled.
Data Source
AI summary
There is provided a semiconductor device with improved integration and performance. The semiconductor device includes a substrate, a first lower active pattern, a first upper active pattern on the first lower active pattern, a first gate structure on the first lower active pattern and the first upper active pattern, a second lower active pattern spaced apart from the first lower active pattern, a second upper active pattern on the second lower active pattern and spaced apart from the first upper active pattern, a second gate structure on the second lower active pattern and the second upper active pattern, a first source/drain contact electrically connected to a first lower source/drain region of the first lower active pattern and a first upper source/drain region of the first upper active pattern and a first back connecting wire and electrically connecting the first source/drain contact and the second gate structure.