Stacked Multi-Gate Contact Structure With Selective Silicide Deposition
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Solution Overview
Problem
Existing stacked multi-gate devices face challenges in reducing contact resistance due to the formation of long source/drain contacts and small contact areas, particularly in complementary field effect transistors (C-FETs), which increase resistance and hinder performance.
Innovation Solution
A method involving selective deposition of a first silicide layer on p-type source/drain features using metal precursors that react with silicon germanium surfaces, and optionally using a self-assembled monolayer to inhibit deposition on germanium-free surfaces, followed by a global n-type dipole layer and a second silicide layer to reduce contact resistance across both p-type and n-type features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If long source/drain contacts are formed in stacked multi-gate devices, then device density is increased, but contact resistance increases
Solution Approach 1:
The contact structure is segmented into multiple portions: a first portion within the trench contact extending through the first source/drain feature, and a second portion within the second source/drain feature. This segmentation allows each portion to be optimized independently, reducing overall contact resistance while maintaining high device density through the vertical stacked configuration
Solution Approach 2:
The patent transitions from planar contacts to vertical three-dimensional contacts that extend through stacked source/drain features. The contact structure utilizes the vertical dimension by forming a trench contact that penetrates through multiple layers, thereby reducing contact resistance without increasing lateral footprint and maintaining high device density
2Productivity
If contact area is reduced to increase device density, then more devices fit per chip area, but contact resistance increases
Solution Approach 1:
The contact structure exploits the vertical dimension by forming a trench contact that extends downward through stacked source/drain features. This vertical extension increases the effective contact area and reduces contact resistance without increasing the lateral contact footprint, thereby maintaining high device density
3Reliability
If selective silicide deposition is performed on p-type source/drain features, then contact resistance is reduced, but process complexity increases
Solution Approach 1:
A self-assembled monolayer is used as an intermediary blocking layer that selectively prevents silicide deposition on n-type source/drain features while allowing deposition on p-type features. This intermediary layer simplifies the selective deposition process by providing automatic selectivity based on surface chemistry, reducing the need for complex process control
Solution Approach 2:
The patent changes the chemical state of surfaces by forming a self-assembled monolayer on n-type source/drain features. This parameter change (surface chemistry modification) creates selective reactivity that enables automated selectivity during silicide deposition, reducing process complexity while achieving low contact resistance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces contact resistance to below 1×10−9 ohm-cm², enhancing the performance of stacked multi-gate devices by improving conductivity and reducing leakage.
Implementation Method 1
selective deposition of a first silicide layer on p-type source/drain features using metal precursors that react with silicon germanium surfaces
Implementation Method 2
optionally using a self-assembled monolayer to inhibit deposition on germanium-free surfaces
Implementation Method 3
a self-assembled monolayer to inhibit deposition on germanium-free surfaces
Implementation Method 4
The method effectively reduces contact resistance to below 1×10−9 ohm-cm², enhancing the performance of stacked multi-gate devices by improving conductivity
Data Source
AI summary
Method to form low-contact-resistance contacts to source/drain features are provided. A method of the present disclosure includes receiving a workpiece including an opening that exposes a surface of an n-type source/drain feature and a surface of a p-type source/drain feature, selectively depositing a first silicide layer on the surface of the p-type source/drain feature while the surface of the n-type source/drain feature is substantially free of the first silicide layer, depositing a metal layer on the first silicide layer and the surface of the n-type source/drain feature, and depositing a second silicide layer over the metal layer. The selectively depositing includes passivating the surface of the surface of the n-type source/drain features with a self-assembly layer, selectively depositing the first silicide layer on the surface of the p-type source/drain feature, and removing the self-assembly layer.