Stacked NAND Memory Assembly With Etch-Stop Intermediate Level
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Solution Overview
Problem
Existing NAND architecture and fabrication methods face challenges in maintaining structural integrity and performance due to issues like material shaving during misaligned etching processes, leading to impaired device functionality.
Innovation Solution
The development of integrated assemblies with stacked decks, where misaligned etching is mitigated by using a conductive material as an etch stop, forming pillar openings through multiple decks, and replacing certain materials with conductive components to create vertically aligned memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If misaligned etching is performed to form openings through stacked decks, then productivity is improved by enabling parallel processing, but manufacturing precision deteriorates due to material shaving and alignment errors
Solution Approach 1:
The patent introduces an etch stop layer as an intermediary between the decks being etched. This etch stop layer acts as a reference plane that prevents material from underlying decks from being shaved during the etching process, thereby maintaining alignment precision while enabling parallel etching of multiple decks to improve productivity
Solution Approach 2:
The etch stop layer is formed in advance before the misaligned etching process. By preliminarily establishing this protective layer at the correct depth, the subsequent etching operations can proceed in parallel without risking material damage to underlying structures, thus resolving the contradiction between productivity and precision
2Device complexity
If conventional etching processes are used without etch stop layers, then device complexity is reduced by simplifying the fabrication process, but reliability deteriorates due to material loss and structural damage
Solution Approach 1:
The etch stop layer serves as a protective intermediary that prevents harmful etching effects from reaching underlying sensitive structures. This additional layer, while adding some fabrication steps, ensures reliable device functionality by preventing material loss and structural damage during the etching process
3Manufacturing precision
If aligned etching is performed sequentially through each deck, then manufacturing precision is maintained, but productivity deteriorates due to sequential processing requirements
Solution Approach 1:
The etch stop layer enables a transition from sequential to parallel processing by acting as a protective barrier. With this intermediary in place, multiple decks can be etched simultaneously with misaligned openings without risking damage to underlying structures, thus maintaining precision while dramatically improving productivity
Solution Approach 2:
The patent introduces flexibility in the etching process by allowing misaligned openings in different decks. The etch stop layer dynamically adapts to accommodate these misalignments, enabling parallel processing while maintaining the integrity of the overall structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the structural integrity and performance of NAND memory devices by preventing material loss and ensuring proper alignment of memory cell structures, thereby improving device reliability and functionality.
Implementation Method 1
misaligned etching is mitigated by using a conductive material as an etch stop
Implementation Method 2
replacing certain materials with conductive components to create vertically aligned memory cells
Data Source
AI summary
Some embodiments include an integrated assembly having a second deck over a first deck. The first deck has first memory cell levels, and the second deck has second memory cell levels. A pair of cell-material-pillars pass through the first and second decks. Memory cells are along the first and second memory cell levels. The cell-material-pillars are a first pillar and a second pillar. An intermediate level is between the first and second decks. The intermediate level includes a region between the first and second pillars. The region includes a first segment adjacent the first pillar, a second segment adjacent the second pillar, and a third segment between the first and second segments. The first and second segments include a first composition, and the third segment includes a second composition different from the first composition. Some embodiments include methods of forming integrated assemblies.