3D Stacked NAND Flash Memory With Segmented Interconnects
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Solution Overview
Problem
Current semiconductor memory devices fail to meet the requirements of high speed, high storage density, and low bit cost, making them unsuitable for modern data handling needs.
Innovation Solution
A semiconductor memory device with a three-dimensionally stacked NAND flash memory configuration, including a specific interconnecting layer and signal line structure, and a readout circuit unit that optimizes data storage and retrieval operations by controlling voltage and current paths within the memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional semiconductor memory device structure is used, then manufacturing and operation are simpler, but storage density and speed requirements cannot be met
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell arrangement to a three-dimensional stacked configuration with multiple interconnecting layers (first through seventh interconnecting layers) extending in different directions. This vertical stacking enables significantly higher storage density by utilizing the third dimension (stacking direction) while maintaining manufacturability through systematic layer formation processes.
Solution Approach 2:
The patent implements a nested structure where multiple interconnecting layers are stacked vertically, with signal lines extending through multiple layers. The first through seventh interconnecting layers are nested in the stacking direction, creating a compact three-dimensional architecture that achieves high storage density within a small footprint while maintaining structural organization.
2Measurement precision
If channel resistance is not minimized, then device structure is simpler, but reading accuracy and speed are degraded
Solution Approach 1:
The patent divides the interconnecting structure into multiple separate layers (first through seventh interconnecting layers) with distinct functions. Signal lines are segmented across these layers, with specific layers dedicated to word lines, bit lines, and control gates. This segmentation reduces resistance by providing multiple parallel conduction paths while maintaining structural simplicity through modular layer design.
Solution Approach 2:
The patent uses vertical stacking of interconnecting layers to reduce channel resistance. By extending signal lines through multiple stacked layers rather than relying on single-plane traces, the invention creates three-dimensional conduction paths that reduce resistance and improve reading accuracy without significantly increasing planar device footprint.
3Quantity of substance
If high storage density is achieved through three-dimensional stacking, then bit cost is reduced, but device complexity increases
Solution Approach 1:
The patent implements multi-functional interconnecting layers that serve multiple purposes. For example, the third interconnecting layer functions as both a word line and a control gate for specific memory cells. This universality allows the same structural elements to perform multiple functions, reducing the total number of separate components needed and thereby reducing overall device complexity while maintaining high storage density.
Solution Approach 2:
The patent merges certain interconnecting layer functions to reduce complexity. The third interconnecting layer is combined to serve as both a word line for accessing memory cells and a control gate for selecting specific cells. This merging of functions reduces the total number of separate interconnecting layers needed, making the high-density three-dimensional structure more manageable and manufacturable.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: a first interconnecting layer; a first signal line; a first memory cell that stores first information between the first interconnecting layer and the first signal line; second to fourth interconnecting layers provided above the first interconnecting layer; fifth to seventh interconnecting layers disposed apart from the second to fourth interconnecting layers; a second signal line coupled to the first signal line; a third signal line coupled to the first and second signal lines and the sixth interconnecting layer; and, first to fifth transistors.