Stacked NAND Circuit Layout for Strong Linear Current Drive
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Solution Overview
Problem
Conventional NAND circuits with stacked asymmetric FETs suffer from linear current degradation due to weak drain overlap, which degrades performance by increasing drain external resistance and reducing linear current drive, especially when the top circuit is switched.
Innovation Solution
A stacked structure comprising an asymmetric FET at the top and a symmetric FET at the bottom, where the symmetric FET is connected to ground, allowing for saturated current drive capabilities during saturation mode while avoiding linear current degradation during linear mode operation, thereby enhancing top switch speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If asymmetric FETs are used in stacked configuration, then saturated current drive capabilities and low Miller capacitance are achieved, but linear current degradation occurs due to weak drain overlap
Solution Approach 1:
The patent applies local quality by using asymmetric FETs specifically at the top of the stack where low Miller capacitance and saturated current drive are critical, while using symmetric FETs at the bottom where linear current drive is more important. This localized differentiation optimizes each position's contribution to overall circuit performance.
Solution Approach 2:
The stacked FET configuration is segmented into two distinct types: asymmetric FETs at the top and symmetric FETs at the bottom. This segmentation allows each segment to be optimized for its specific functional requirements, with asymmetric devices providing low capacitance for switching speed and symmetric devices providing strong linear current drive.
2Speed
If asymmetric FETs are used at the bottom of the stack, then node capacitance is reduced, but drain external resistance increases due to weak drain overlap
Solution Approach 1:
The patent applies local quality by using asymmetric FETs specifically at the top of the stack where low Miller capacitance and saturated current drive are critical, while using symmetric FETs at the bottom where linear current drive is more important. This localized differentiation optimizes each position's contribution to overall circuit performance.
3Adaptability or versatility
If stacked configuration is used, then NAND logic function is achieved, but linear mode performance degrades due to weak current overlap
Solution Approach 1:
The patent applies local quality by using asymmetric FETs specifically at the top of the stack where low Miller capacitance and saturated current drive are critical, while using symmetric FETs at the bottom where linear current drive is more important. This localized differentiation optimizes each position's contribution to overall circuit performance.
Solution Approach 2:
The stacked FET configuration is segmented into two distinct types: asymmetric FETs at the top and symmetric FETs at the bottom. This segmentation allows each segment to be optimized for its specific functional requirements, with asymmetric devices providing low capacitance for switching speed and symmetric devices providing strong linear current drive.
Data Source
AI summary
An NAND circuit has a stacked structure having at least one symmetric NFET at a bottom of the stack. More particularly, the circuit has a stacked structure which includes an asymmetric FET and a symmetric FET. The symmetric FET is placed at the bottom of the stacked structure closer to ground than the asymmetric FET.