3D Stacked NAND Memory Architecture for Lower-Cost Storage
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Solution Overview
Problem
Existing memory devices face challenges in reducing production costs while maintaining performance and efficiency.
Innovation Solution
A memory device is designed with a stacked structure of CMOS circuits on multiple substrates, incorporating a memory cell array connected to CMOS circuits, and includes a circuit configuration with row and sense amplifier modules to enhance data storage and retrieval capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a NAND flash memory structure is used, then data storage capability is improved, but production cost reduction is limited
Solution Approach 1:
The patent transitions from planar 2D memory architecture to three-dimensional stacked architecture, where memory cells are arranged vertically across multiple substrates. This dimensional change increases storage density without proportionally increasing manufacturing complexity, as the stacking approach allows for standardized substrate processing and bonding techniques.
Solution Approach 2:
The memory device is divided into multiple independent substrates (first substrate, second substrate, third substrate) that can be manufactured separately and then bonded together. This segmentation enables modular production, where each substrate can be optimized and fabricated using standard processes, reducing overall production costs while achieving high storage capacity.
2Ease of manufacture
If multiple substrates are stacked, then production cost is reduced, but device complexity increases
Solution Approach 1:
The patent employs universal bonding interfaces and standardized substrate designs that can be applied across multiple memory devices. The bonding structures and circuit interconnections follow consistent patterns that simplify the manufacturing process despite the increased number of substrates, making the complex stacked architecture scalable and manufacturable.
3Productivity
If CMOS circuits are integrated on multiple substrates, then data retrieval efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent introduces bonding structures as intermediary elements that connect CMOS circuits across different substrates. These bonding interfaces serve as mediators for signal and power transmission, enabling efficient data retrieval operations while isolating the manufacturing complexity to standardized bonding processes rather than requiring complex integration of all circuits in a single substrate.
Data Source
AI summary
According to one embodiment, a memory device includes a first silicon substrate, a second silicon substrate, and a memory cell array. A first CMOS circuit is formed on the first silicon substrate. The second silicon substrate is provided above the first silicon substrate in a stacking direction. A second CMOS circuit is formed on the second silicon substrate. The memory cell array is provided above the second silicon substrate in the stacking direction. The memory cell array is connected to the first CMOS circuit and the second CMOS circuit and includes a plurality of memory cells arranged in the stacking direction of the first silicon substrate and the second silicon substrate.