3D Stacked NAND Memory Architecture for AI Data Throughput
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Solution Overview
Problem
Existing memory devices struggle to achieve high density and small dimensions while meeting the increasing demands of storage capacity and performance, particularly in applications like artificial intelligence and deep learning.
Innovation Solution
A memory device architecture that includes a first memory chip with high-speed operation and a stack of second memory chips with higher memory density, specifically using NAND architecture, which are electrically connected to a controller chip and a processor chip. This configuration allows for efficient data transfer and reduced memory speed requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory device uses traditional single-layer structure, then manufacturing is simpler, but memory density is insufficient
Solution Approach 1:
The patent transitions from a traditional single-layer planar memory structure to a three-dimensional stacked structure. Multiple memory chips are vertically stacked and interconnected through conductive vias and bumps, effectively utilizing the Z-dimension to increase memory density without expanding the device footprint. This dimensional transformation directly resolves the contradiction by providing higher storage capacity while maintaining manufacturing feasibility through established 3D integration techniques.
2Quantity of substance
If memory device increases storage capacity, then it meets application demands, but device dimension increases
Solution Approach 1:
The invention stacks multiple memory chips vertically to increase storage capacity within a compact footprint. By utilizing the vertical dimension rather than expanding horizontally, the device achieves high storage capacity while maintaining small device dimensions. The stacked architecture with inter-chip connections enables dense integration without proportionally increasing the overall device volume.
3Quantity of substance
If memory device uses high-density NAND architecture, then memory density increases, but data transfer speed decreases
Solution Approach 1:
The memory system is segmented into multiple independent memory chips stacked vertically, each capable of parallel data transfer operations. The controller chip independently manages data flow to and from each memory chip through separate I/O interfaces. This segmentation enables parallelism in data transfer, compensating for the inherently slower speed of high-density NAND architecture by utilizing multiple concurrent data paths, thereby achieving both high density and acceptable transfer speeds.
Solution Approach 2:
The system changes the parameter of data transfer by utilizing multiple I/O interfaces and parallel data paths across stacked memory chips. Instead of relying on a single high-speed interface, the controller employs multiple simultaneous data channels, effectively increasing the aggregate data transfer rate. This parameter change allows the system to maintain high data throughput despite using high-density NAND architecture with inherently lower per-channel transfer speeds.
Data Source
AI summary
A memory device for artificial intelligence calculation includes a memory structure, a controller chip, and a processer chip. The memory structure includes a first memory chip, and a stack of second memory chips, in which a memory density of each of the second memory chips is greater than a memory density of the first memory chip. The controller chip is electrically connected to the first memory chip and the second memory chips. The processer chip is electrically connected to the controller chip.