Stacked NAND Memory Read Current Enhancement
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Solution Overview
Problem
As semiconductor pillars in stacked type semiconductor memory devices are downscaled for increased integration, the on-current of the read operation decreases, making it difficult to accurately read data.
Innovation Solution
The semiconductor memory device employs a drive circuit that applies specific potentials to different memory cell transistors in parallel NAND strings, including a read potential to obliquely-positioned cells and a counter potential to opposing cells, to increase the on-current while maintaining accurate threshold determination of selected cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor pillars are downscaled to increase integration, then integration density is improved, but on-current during read operation decreases
Solution Approach 1:
The patent applies different potentials to different groups of memory cell transistors based on their spatial positions. Specifically, obliquely-positioned cells receive a read potential while opposing cells receive a counter potential, creating localized electrical conditions that enhance the on-current of selected cells without affecting the overall device scaling. This local differentiation resolves the contradiction by maintaining sufficient read current in scaled-down devices through targeted potential application.
Solution Approach 2:
The patent changes the electrical parameters (potentials) applied to memory cell transistors during read operations. By dynamically adjusting the gate potentials of opposing cells to a counter potential while applying read potential to obliquely-positioned cells, the system optimizes the on-current characteristics. This parameter modulation allows accurate data reading even when semiconductor pillars are downscaled, thus resolving the contradiction between integration density and on-current.
2Quantity of substance
If semiconductor pillars are downscaled to increase integration, then integration density is improved, but data reading accuracy decreases
Solution Approach 1:
The patent implements local quality control by applying different potentials to different spatial groups of memory cells. Obliquely-positioned cells are subjected to read potential while opposing cells receive counter potential, creating localized electrical environments that enhance signal differentiation. This spatially-selective potential application maintains measurement precision for threshold determination even in downscaled devices with reduced on-current.
Solution Approach 2:
The patent utilizes parameter changes in gate potentials to improve measurement precision. By switching opposing cells to a counter potential during read operations, the system creates a reference state that enhances the detectability of threshold changes in selected cells. This dynamic parameter adjustment compensates for the reduced signal strength in downscaled pillars, maintaining accurate data reading capability.
3Reliability
If specific potentials are applied to different memory cell transistors, then on-current is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory cell array into distinct groups based on their positional relationships (obliquely-positioned cells versus opposing cells). Each segment is controlled by separate potential application circuits that can independently set read potential or counter potential. This segmentation allows complex potential control to be broken down into manageable, modular control units, reducing the overall device complexity while maintaining enhanced on-current performance.
Solution Approach 2:
The patent implements multi-functional control circuits that can apply different potentials (read potential and counter potential) using the same basic circuit architecture. The control mechanism serves multiple functions: selecting target cells, applying appropriate potentials, and timing the operations. This universality reduces the need for separate dedicated circuits for each function, thereby limiting the increase in device complexity while achieving improved on-current through differential potential application.
Data Source
AI summary
A semiconductor memory device includes a first NAND string and a second NAND string sharing a channel and being connected in parallel. When reading a value from a first memory cell transistor of the first NAND string, a first potential is applied to a gate of a second memory cell transistor of the first NAND string and a gate of at least one of fourth memory cell transistors opposing the second memory cell transistor, a second potential is applied to a gate of a third memory cell transistor of the second NAND string opposing the first memory cell transistor, and a gate potential of the first memory cell transistor is swept between the second potential and the first potential. The second potential is lower than the first potential.