Stacked NAND Memory Layout for Faster Sense Amplifier Access
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Solution Overview
Problem
Existing NAND flash memory devices face challenges in efficiently accessing and reading data from memory cells due to limitations in their architectural design, which affects performance and efficiency.
Innovation Solution
The memory device incorporates a novel architecture where a substrate with memory cells is bonded to a substrate with CMOS circuits, featuring a sense amplifier module with shifted sense amplifier regions and transfer regions, allowing for improved data access and reading capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional NAND flash memory architecture is used, then the device structure is simple, but data access and reading efficiency are limited
Solution Approach 1:
The memory device is divided into two separate substrates: a first substrate containing memory cells and a second substrate containing CMOS circuits. This segmentation allows independent optimization of each substrate's function, enabling improved data access efficiency through specialized sense amplifier regions while maintaining manageable overall device complexity through modular architecture.
Solution Approach 2:
The patent transitions from a planar single-substrate architecture to a three-dimensional stacked architecture where memory and CMOS circuits are vertically integrated on separate substrates. This dimensional change enables overlapping of functional regions (sense amplifier regions overlapping memory regions) that would be impossible in a two-dimensional layout, thereby improving data access efficiency without proportionally increasing footprint area.
2Reliability
If memory and CMOS circuits are integrated on the same substrate, then device complexity is reduced, but data reading performance is compromised
Solution Approach 1:
By separating memory cells and CMOS circuits onto different substrates, each substrate can be independently optimized for its specific function. The first substrate is optimized for memory storage with specialized structures, while the second substrate is optimized for signal processing with sense amplifier modules, thereby improving data reading performance without requiring complex co-integration of conflicting functional requirements on a single substrate.
Solution Approach 2:
The patent introduces a bonding interface between the first substrate (memory) and second substrate (CMOS) as an intermediary connection. This bonding structure enables high-performance electrical coupling between memory cells and sense amplifiers while maintaining physical separation of the two functional domains, thus achieving improved reading performance without the complexity of monolithic integration.
3Speed
If sense amplifier regions are positioned directly over memory regions, then data reading speed is improved, but manufacturing alignment precision requirements increase
Solution Approach 1:
The bonding pads on the first substrate are divided into multiple regions, with some bonding pads positioned to overlap sense amplifier regions on the second substrate. This segmentation of bonding pad locations allows selective electrical coupling between memory cells and sense amplifiers, enabling fast data reading through optimized signal paths while distributing alignment requirements across multiple discrete bonding interfaces rather than requiring perfect alignment across the entire overlapping region.
Data Source
AI summary
A memory device includes a memory layer and a circuit layer. The memory layer includes first to third regions arranged in a first direction. The circuit layer includes first and second transfer regions, and first and second sense amplifier regions. The first and second transfer regions are shifted in the first direction and arranged in a second direction. In a third direction, the first sense amplifier region overlaps the first region, and the second sense amplifier region overlaps the second region. The first sense amplifier region and the first transfer region are arranged in the first direction, and the second sense amplifier region and the second transfer region are arranged in the first direction.