3D Stacked NAND Memory With Shared Circuits for Smaller Chip Area
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices face challenges in managing chip area increases due to complex circuit configurations.
Innovation Solution
A semiconductor memory device with a three-dimensional stacked NAND flash memory structure, comprising multiple array chips and a circuit chip, where memory cells are connected via shared word lines and independent bit lines, allowing concurrent processing of data across multiple memory cell arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory cell arrays are configured with independent circuits, then data processing capability is improved, but chip area increases
Solution Approach 1:
Multiple memory cell arrays share common circuits including word line drivers, bit line drivers, and sense amplifiers. This merging of circuit resources allows multiple arrays to be processed concurrently without proportionally increasing chip area, as the shared circuits serve multiple arrays simultaneously.
Solution Approach 2:
The common circuits are designed with universal functionality to handle multiple memory cell arrays. Word line drivers can drive word lines across different arrays, bit line drivers can serve multiple bit lines, and sense amplifiers can read from multiple memory cells, enabling one circuit to perform multiple functions across different arrays.
2Area of stationary object
If shared circuits are used among multiple memory cell arrays, then chip area is reduced, but circuit complexity increases
Solution Approach 1:
The memory system is segmented into multiple independent memory cell arrays that can be independently selected and accessed. Each array has its own memory cells and local connections, while sharing higher-level control circuits. This segmentation allows the complexity to be distributed and managed through selective activation of specific arrays based on operation needs.
Solution Approach 2:
The circuit configuration is made dynamic through selective connection and activation. Different memory cell arrays can be selectively connected to the shared circuits based on the specific operation required. This dynamic reconfiguration allows the system to adapt its complexity level to the actual operational needs, activating only the necessary circuits for each task.
Data Source
AI summary
A semiconductor memory device includes first, second, and third chips. The first chip includes a first memory cell. The second chip includes a second memory cell. The third chip includes a row decoder and a sense amplifier. The first and second memory cells are commonly connected to the row decoder via a first word line. The first and second memory cells are connected to the sense amplifier via first and second bit lines, respectively. The sense amplifier includes a first node selectively connectable to the first and second bit lines. The sense amplifier is configured to sense a voltage at the first node to read data in the first memory cell when the first node is connected to the first bit line and sense the voltage at the first node to read data in the second memory cell when the first node is connected to the second bit line.